Gain an understanding of the fundamental topics and concepts of computer architecture including the application of these with modern Arm processors

A textbook on understanding system on chip design

A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )

This repository contains the complete Verilog implementation and supporting tools for a cycle-accurate, dual-issue pipelined multimedia processor inspired by the Synergistic Processing Unit (SPU) of the Cell Broadband Engine architecture.

VHDL , ModelSIM, Quartus, FPGA, Image Processing

The Sherwood Architecture is a custom 64-Bit RISC based CPU architecture.

An analysis of intels goldmont plus uarch predecode caches core logic due to it being undocumented

Μια ενδεικτική υλοποίηση RISC-V επεξεργαστή και ενός υποστηρικτικού Assembler - Διπλωματική εργασία στο Τμήμα Μηχανικών Η/Υ και Πληροφορικής, Πανεπιστήμιο Πατρών / An Indicative RISC-V CPU Implementation and an Accompanying Assembler - Master's Diploma Thesis at the Computer Engineering and Informatics Department (CEID), University of Patras

Single-Cycle RISC-V Processor using SystemVerilog on a Nexys A7 (Artix-7) FPGA. Project includes complete datapath and control logic with instruction memory, data memory, ALU, immediate generator, and branch comparator. It supports the complete RV32I instruction set (R, I, S, B, U, J types).

Assembler, ISA & everything else featuring the 16-Bit Minecraft Redstone CPU "Frostybte"

A Verilog project for designing an Arithmetic Logic Unit (ALU) using pre-existing logic blocks. This ALU performs fundamental operations such as addition, subtraction, and logical shifts in a CPU architecture.

Code snippets for the CpuFun blog

[2009 – 2012] MDSP: functional simulation of a Multimedia Digital Signal Processor

[Computer Engineering] Programmable 8-bit computer based on von Neumann architecture, designed and implemented from scratch in Logisim.

A study in MIPS microarchitecture trade-offs. This project implements three CPU designs: a single-cycle, a hardware-scheduled multicycle, and a software-scheduled pipelined core; then documents and contrasts their performance/complexity. Source is organized by variant (src_sc, src_hw, src_sw) with dedicated testbenches and write-ups.

This is a simple CPU emulator with custom architecture

📱 An app to view all supported ABI of the running device

General purpose processor with a RISC architecture and a five stage pipeline, implemented on a Cyclone IV FPGA using a development board

16-bit CPU architecture implementation and verification using SystemVerilog

CPU Cache Simulation using gem5