This repository contains a series of Verilog codes for the course UE22CS251A (DDCO).
-
Updated
Nov 13, 2024 - Verilog
#
ddco
Here are 6 public repositories matching this topic...
This repo consists of the iverilog implementation of a Parallel Prefix adder - 8bit (I/P - O/P). This was done as a part of a project Under UE19CS206 - Digital Design and Computer Organization Laboratory Course at PES University.
-
Updated
Jan 6, 2021 - Verilog
Digital Design and Computer Organisation Mini-project
arm fpga project verilog college-project digital-design computer-organization prbs-generator mini-project sequence-generation pseudo-random-generator field-programmable-gate-arrays verilog-project sequence-generator prbs ddco arm7tdmi digital-design-and-computer-organization binary-sequence-generator
-
Updated
Aug 7, 2023 - Verilog
Laboratory Mini Project for the Course - Digital Design and Computer Organization (UE22CS251A)
-
Updated
Dec 22, 2023 - Verilog
Improve this page
Add a description, image, and links to the ddco topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with the ddco topic, visit your repo's landing page and select "manage topics."