An interactive course on computer science and digital architecture, built from the ground up. (Minecraft and CircuitVerse tracks available)
We implemented a single cycle version of the MIPS CPU in VHDL code, under the simplification of 1 cycle memory delay, a reduced instruction set defined by the assignment, and 10-bit memory space. We then used the Quartus FPGA chipset to verify the design. By David Shmailov and Aviram Lachmani
This repository is to communicate and promote the Dragon1 Open Standard for Architecture Modeling, with the Dragon1 Modeling Language. This repository will specify the modeling language and interchange file format, provide 100 example models and diagrams to help architects and designers with their tasks. https://www.dragon1.com
Chocolatey nupkg recipe for Digital logic designer and circuit simulator
My bachelor's thesis @Units
Add a description, image, and links to the digital-architecture topic page so that developers can more easily learn about it.
To associate your repository with the digital-architecture topic, visit your repo's landing page and select "manage topics."