RTL description, synthesis and physical design of a 4-stage pipelined 32bit RISC processor
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Updated
Dec 22, 2022 - Verilog
RTL description, synthesis and physical design of a 4-stage pipelined 32bit RISC processor
DLX microprocessor described in VHDL for the Microelectronic Systems course @ Politecnico di Torino
Digital design and synthesis of a DLX processor in VHDL
DLX architecture simulator written in TypeScript & React
Emulator for the DLX-Processor
Optimization of matrix computation in a low-level language
SDLX - Simplified DLX processor in Verilog
Implementacion de la práctica desarrollada de WinDLX a lo largo del curso 23-24 de Arquitectura de Computadores (USAL)
Computer Architectures - Practical Assignment #2:
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