A VHDL code base that contains Utility Packages for both HDL and Testbenches
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Updated
Aug 19, 2025 - VHDL
A VHDL code base that contains Utility Packages for both HDL and Testbenches
Reusable HDL modules, packages, and testbench utilities for FPGA and ASIC development, supporting both VHDL and Verilog.
Fully functional RISC-V compatible multicycle CPU built in Verilog. Includes ALU, datapath, FSM controller, memory, and testbenches.
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