C++ Instruction Set Simulator for RISC-V RV32IMC & custom SIMD instructions with cache and branch predictor models, C/ASM workloads, and Python analysis tools
emulator cache simd riscv performance-visualization performance-analysis risc-v instruction-set-simulator cache-simulator baremetal branch-prediction coremark rv32i branch-predictor dhrystone rv32im rv32imc riscv-emulator dpi-c embench
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Updated
Nov 7, 2025 - C++