#
floating-point-multiplication
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6 public repositories
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Hardware designs modelled with verilog
Updated
Mar 9, 2021
Verilog
Updated
Jun 22, 2020
Verilog
Floating point multiplier with rounder, exception handler and assertions in SystemVerilog. Project is part of class HW-2, ECE AUTH.
Updated
Jun 3, 2024
SystemVerilog
An efficient multi-format low-precision floating-point multiplier
Updated
Apr 4, 2024
Verilog
Updated
Mar 20, 2019
Python
A detailed and commented floating point multiplier code for a standard ARM architecture.
Updated
Oct 5, 2020
Assembly
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