esp32でmmd

IEEE 754 single and double precision floating point library in systemverilog and vhdl

Wrappers for open source FPU hardware implementations.

Chisel library for Unum Type-III Posit Arithmetic

IEEE 754 single precision floating point library in systemverilog and vhdl

A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA

A chisel3 wrapper for pulp-platform/fpnew

6-stage in-order dual-issue superscalar risc-v cpu with floating point unit

This repository contains an assembly program written in AT&T syntax called FPU-Analyzer. The program analyzes a series of floating-point numbers and calculates their sum and average.

X86-64 bilateral instruction tokenizer implemented in C. Supports the following processor extensions: AES, AVX, AVX2, AVX512, FMA, MMX, SSE, SSE2, SSE3, SSE4, x87(FPU), VMX. In order to ease testing, a diassembler which transforms tokens into compilable assembly (for NASM compiler) has been implemented.

Laboratory works with Assembly x86 (NASM) using Linux.

Double Extended precision FPU calculator (80 bits)

Proof of concept connecting ATmega644 with the good old 80287 math coprocessor

DCPU-16 emulator

Mirror of https://coe.northeastern.edu/Research/rcl/projects/floatingpoint/index.html

drivers for multiple peripheral of the SAME70Q21 made for the XPLD board

MIPS-like CPU , an FPU, a compiler and a simulator for running ray-tracing program

Домашние работы по курсу "Ассемблер" в ИТМО

Specialized FPU for Fast Inverse Square Root Algorithm

Simulation model of a mathematical processor (Floating point unit, FPU)