6-stage in-order dual-issue superscalar risc-v cpu with floating point unit

IEEE 754 single precision floating point library in systemverilog and vhdl

IEEE 754 single and double precision floating point library in systemverilog and vhdl

Fully synthesizable and paramterizable, IEEE-754 compliant Floating Point Unit (FPU) in systemverilog. Supports fused multiply add, division and square root operations.

Simple Floating Point Unit in MBF40bits (9-digits Basic) for a Z80 processor in Verilog

Wrappers for open source FPU hardware implementations.

Chisel library for Unum Type-III Posit Arithmetic

A simple Floating-Point arithmetic unit - implemented in SystemVerilog

Computer Architecture - Informatyka PG 2022/2023 - labs & notes

A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA

This repository contains an assembly program written in AT&T syntax called FPU-Analyzer. The program analyzes a series of floating-point numbers and calculates their sum and average.

Pi Calculator (automatically exported from code.google.com/p/pi-calc)

Double Extended precision FPU calculator (80 bits)

In this project we have implemented Add/Minus unit and operations in a Floating-Point unit

MIPS-like CPU , an FPU, a compiler and a simulator for running ray-tracing program

Simulation model of a mathematical processor (Floating point unit, FPU)

Specialized FPU for Fast Inverse Square Root Algorithm

X86-64 bilateral instruction tokenizer implemented in C. Supports the following processor extensions: AES, AVX, AVX2, AVX512, FMA, MMX, SSE, SSE2, SSE3, SSE4, x87(FPU), VMX. In order to ease testing, a diassembler which transforms tokens into compilable assembly (for NASM compiler) has been implemented.

Programming assignments in university course "System Programming"