Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130

This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK

In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transfer Level (RTL) to the Graphical Data System (GDS)

The SAP-1 in Verilog, and now as an ASIC!

Report of the contents learned in the 5-day workshop by VSD regarding the open-source EDA tools in the VLSI industry

2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organized by VSD in collaboration with NASSCOM (Advanced Physical Design using OpenLANE /Sky130)

This repository offers a compact design verification flow using OpenLANE. Scripts cover synthesis correctness, functional and power verification, DRC/LVS, timing analysis, and reliability checks. Contributions are welcome.

Characterised a standard inverter and adding to the openlane flow

This is my openlane repository in which we perform synthesis of our design/module.

Complete RTL to GDSII flow of a picorv32a core

VSDMemSOC Implementation flow:: RTL2GDSII