System Reset Controller (sysrst_ctrl) that provides programmable hardware-level responses to trusted IOs and basic board-level reset sequencing capabilities

Analog to Digital Converter Control Interface

OpenTitan Rv Core Ibex IP block

The mailbox IP block in the OpenTitan Integrated design implements a request-response channel that the host System-on-Chip (SoC) may use to request security ser

Keccak Message Authentication Code (KMAC) and Secure Hashing Algorithm 3 (SHA3)

This document specifies the OTP MACRO hardware IP functionality.

ROM controller (rom_ctrl) is the connection between the chip and its ROM

Cryptographically Secure Random Number Generator (CSRNG)

OpenTitan UART IP - Full duplex serial communication peripheral with programmable baud rate, RX/TX buffers, and interrupt support

OpenTitan Prim Generic IP block

I2C controller

OpenTitan Flash Ctrl IP block

Entropy Distribution Network (EDN) interfaces to the CSRNG IP module

SRAM memory controller

Debugging in RISC-V can be done using one of the following mechanisms:

OpenTitan Prim Xilinx IP block

RISC-V Debug System wrapper functionality

Entropy Source: interface to an external physical random noise generator

OpenTitan Keymgr Dpe IP block

The Direct Memory Access (DMA) controller is a peripheral within the OpenTitan system-on-chip (SoC).