parameterised-verilog

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Sooryakiran / dotV

A library to generate parameterized Verilog code from C++. Allows you to assemble Verilog modules in C++, use C++ syntax to dynamically generate complex connections, parameterize code, and ultimately get the Verilog code automatically generated.

cpp verilog hardware-designs verilog-generator parameterised-verilog

Updated Dec 20, 2020
C++

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parameterised-verilog

Here is 1 public repository matching this topic...

Sooryakiran / dotV

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