Simulation platform that enables VHDL-style C++ coding. VCD generation for easy debug. VHDL code generation using C preprocessor. Simple risc-V rv32i SoC example, + Risc-V test suite and gcc bare-metal example. Linux (or WSL) / clang or gcc / risc-v toolchain / quartus required
c-plus-plus arduino simulator fpga vhdl rtl gtkwave risc-v vcd de10-lite vidor rtl-files rtl-generation
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Updated
May 29, 2021 - C