rtl-to-gds
Here are 6 public repositories matching this topic...
Parameterized N×N output-stationary systolic array accelerator for INT8 neural network inference. Full RTL-to-GDS flow on ASAP7 7nm using Cadence Genus + Innovus. 667 MHz, 42.7 GOPS peak throughput, 0.33 mW/GOP. SystemVerilog RTL, synthesis, place-and-route and self-checking testbench included.
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Feb 18, 2026 - Verilog
ASIC Physical Design of FIFO using Cadence Innovus | Floorplan → CTS → Routing → Timing & Power Analysis
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Mar 18, 2026 - Verilog
Complete RTL-to-GDSII physical design flow of an 8-bit ALU using OpenLane and Sky130 PDK. Includes synthesis, floorplanning, placement, CTS, routing, DRC/LVS signoff, and multi-corner STA.
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Mar 30, 2026 - Verilog
End-to-end Digital VLSI project demonstrating a Full Adder from RTL to GDS using Yosys and OpenROAD, extended with a custom CMOS Full Adder standard cell and system-level evaluation.
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Jan 6, 2026 - Verilog
Complete RTL-to-GDSII flow for 32-tap FIR filter on SKY130 130nm — 33% fewer cells than OpenLane, formally verified (SAT proof), DRC/LVS clean
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Mar 29, 2026 - Verilog
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