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transistor-level

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transistor-simulator

🔥 This project performs a simulation of N and P-type MOSFET transistors. Next, the creation of logic gates is performed using the simulated transistors. Then, a Half-Adder mechanism is created with the logic gates, to later use it in a binary sum algorithm.

  • Updated Oct 17, 2022
  • C

This project was performed on the completion of our B. Tech 4th Semester Summer Training cum Academic Internship Programme on "RISC-V based 32-bit Digital Processor Design using SPICE" under E&ICT Academy IIT Guwahati and Assam Science & Technology University, Guwahati under TEQIP III in association with VLSI Expert

  • Updated Aug 27, 2021

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