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add support for STM32U585 #3404

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merged 2 commits into from
Nov 24, 2023
Merged

add support for STM32U585 #3404

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c30d2b7
feat(core): add support for STM32U585
TychoVrahe Nov 13, 2023
e315a39
fix(core): fix bootloader update on STM32U5
TychoVrahe Nov 16, 2023
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2 changes: 1 addition & 1 deletion core/SConscript.firmware
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Original file line number Diff line number Diff line change
Expand Up @@ -842,7 +842,7 @@ else:
'$DD if=$TARGET of=${TARGET}.p1 skip=0 bs=128k count=6',
'$CP $TARGET ' + BINARY_NAME,
]
elif 'STM32U5A9xx' in CPPDEFINES_HAL:
elif 'STM32U5A9xx' in CPPDEFINES_HAL or 'STM32U585xx' in CPPDEFINES_HAL:
action_bin=[
'$OBJCOPY -O binary -j .vendorheader -j .header -j .flash -j .data -j .sensitive $SOURCE ${TARGET}',
'$HEADERTOOL -h $TARGET ' + ('-D' if not PRODUCTION else ''),
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109 changes: 109 additions & 0 deletions core/embed/boardloader/memory_stm32u58.ld
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Original file line number Diff line number Diff line change
@@ -0,0 +1,109 @@
/* Trezor v2 boardloader linker script */

ENTRY(reset_handler)

MEMORY {
FLASH (rx) : ORIGIN = 0x0C004000, LENGTH = 48K
SRAM1 (wal) : ORIGIN = 0x30000000, LENGTH = 192K - 0x100
BOOT_ARGS (wal) : ORIGIN = 0x3002FF00, LENGTH = 0x100
SRAM2 (wal) : ORIGIN = 0x30030000, LENGTH = 64K
SRAM3 (wal) : ORIGIN = 0x30040000, LENGTH = 512K
SRAM5 (wal) : ORIGIN = 0x30080000, LENGTH = 0K /* SRAM5 is not available */
SRAM6 (wal) : ORIGIN = 0x30080000, LENGTH = 0K /* SRAM6 is not available */
SRAM4 (wal) : ORIGIN = 0x38000000, LENGTH = 16K
}

main_stack_base = ORIGIN(SRAM2) + SIZEOF(.stack); /* 8-byte aligned full descending stack */
_sstack = ORIGIN(SRAM2);
_estack = main_stack_base;

/* used by the startup code to populate variables used by the C code */
data_lma = LOADADDR(.data);
data_vma = ADDR(.data);
data_size = SIZEOF(.data);

/* used by the startup code to populate variables used by the C code */
sensitive_lma = LOADADDR(.sensitive);
sensitive_vma = ADDR(.sensitive);
sensitive_size = SIZEOF(.sensitive);

/* used by the startup code to wipe memory */
sram1_start = ORIGIN(SRAM1);
sram1_end = ORIGIN(SRAM1) + LENGTH(SRAM1);
sram2_start = ORIGIN(SRAM2);
sram2_end = ORIGIN(SRAM2) + LENGTH(SRAM2);
sram3_start = ORIGIN(SRAM3);
sram3_end = ORIGIN(SRAM3) + LENGTH(SRAM3);
sram4_start = ORIGIN(SRAM4);
sram4_end = ORIGIN(SRAM4) + LENGTH(SRAM4);
sram5_start = ORIGIN(SRAM5);
sram5_end = ORIGIN(SRAM5) + LENGTH(SRAM5);
sram6_start = ORIGIN(SRAM6);
sram6_end = ORIGIN(SRAM6) + LENGTH(SRAM6);

/* reserve 256 bytes for bootloader arguments */
boot_args_start = ORIGIN(BOOT_ARGS);
boot_args_end = ORIGIN(BOOT_ARGS) + LENGTH(BOOT_ARGS);

SECTIONS {
.vector_table : ALIGN(512) {
KEEP(*(.vector_table));
} >FLASH AT>FLASH

.text : ALIGN(4) {
*(.text*);
. = ALIGN(4); /* make the section size a multiple of the word size */
} >FLASH AT>FLASH

.rodata : ALIGN(4) {
*(.rodata*);
. = ALIGN(4); /* make the section size a multiple of the word size */
} >FLASH AT>FLASH

.data : ALIGN(4) {
*(.data*);
. = ALIGN(8);
} >SRAM1 AT>FLASH

/DISCARD/ : {
*(.ARM.exidx*);
}

.bss : ALIGN(4) {
*(.bss*);
. = ALIGN(4);
} >SRAM1

.buf : ALIGN(4) {
*(.buf*);
. = ALIGN(4);
} >SRAM1

.stack : ALIGN(8) {
. = 16K; /* Overflow causes UsageFault */
} >SRAM2

.sensitive : ALIGN(8) {
*(.sensitive*);
. = ALIGN(4);
} >SRAM2 AT>FLASH

.fb : ALIGN(4) {
__fb_start = .;
*(.fb1*);
*(.fb2*);
__fb_end = .;
. = ALIGN(4);
} >SRAM3

.boot_args : ALIGN(8) {
*(.boot_command*);
. = ALIGN(8);
*(.boot_args*);
. = ALIGN(8);
} >BOOT_ARGS


/* Hard-coded address for capabilities structure */
.capabilities 0x0C00FF00 : {KEEP(*(.capabilities_section))}
}
106 changes: 106 additions & 0 deletions core/embed/bootloader/memory_stm32u58.ld
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Original file line number Diff line number Diff line change
@@ -0,0 +1,106 @@
/* Trezor v2 bootloader linker script */

ENTRY(reset_handler)

MEMORY {
FLASH (rx) : ORIGIN = 0x0C010000, LENGTH = 128K
SRAM1 (wal) : ORIGIN = 0x30000000, LENGTH = 192K - 0x100
BOOT_ARGS (wal) : ORIGIN = 0x3002FF00, LENGTH = 0x100
SRAM2 (wal) : ORIGIN = 0x30030000, LENGTH = 64K
SRAM3 (wal) : ORIGIN = 0x30040000, LENGTH = 512K
SRAM5 (wal) : ORIGIN = 0x30080000, LENGTH = 0K /* SRAM5 is not available */
SRAM6 (wal) : ORIGIN = 0x30080000, LENGTH = 0K /* SRAM6 is not available */
SRAM4 (wal) : ORIGIN = 0x38000000, LENGTH = 16K
}

main_stack_base = ORIGIN(SRAM2) + SIZEOF(.stack); /* 8-byte aligned full descending stack */
_sstack = ORIGIN(SRAM2);
_estack = main_stack_base;

/* used by the startup code to populate variables used by the C code */
data_lma = LOADADDR(.data);
data_vma = ADDR(.data);
data_size = SIZEOF(.data);

/* used by the startup code to populate variables used by the C code */
sensitive_lma = LOADADDR(.sensitive);
sensitive_vma = ADDR(.sensitive);
sensitive_size = SIZEOF(.sensitive);

/* used by the startup code to wipe memory */
sram1_start = ORIGIN(SRAM1);
sram1_end = ORIGIN(SRAM1) + LENGTH(SRAM1);
sram2_start = ORIGIN(SRAM2);
sram2_end = ORIGIN(SRAM2) + LENGTH(SRAM2);
sram3_start = ORIGIN(SRAM3);
sram3_end = ORIGIN(SRAM3) + LENGTH(SRAM3);
sram4_start = ORIGIN(SRAM4);
sram4_end = ORIGIN(SRAM4) + LENGTH(SRAM4);
sram5_start = ORIGIN(SRAM5);
sram5_end = ORIGIN(SRAM5) + LENGTH(SRAM5);
sram6_start = ORIGIN(SRAM6);
sram6_end = ORIGIN(SRAM6) + LENGTH(SRAM6);

/* reserve 256 bytes for bootloader arguments */
boot_args_start = ORIGIN(BOOT_ARGS);
boot_args_end = ORIGIN(BOOT_ARGS) + LENGTH(BOOT_ARGS);

_codelen = SIZEOF(.flash) + SIZEOF(.data) + SIZEOF(.sensitive);

SECTIONS {
.header : ALIGN(4) {
KEEP(*(.header));
} >FLASH AT>FLASH

.flash : ALIGN(512) {
KEEP(*(.vector_table));
. = ALIGN(4);
*(.text*);
. = ALIGN(4);
*(.rodata*);
. = ALIGN(512);
} >FLASH AT>FLASH

.data : ALIGN(4) {
*(.data*);
. = ALIGN(512);
} >SRAM1 AT>FLASH

/DISCARD/ : {
*(.ARM.exidx*);
}

.bss : ALIGN(4) {
*(.bss*);
. = ALIGN(4);
} >SRAM1

.buf : ALIGN(4) {
*(.buf*);
. = ALIGN(4);
} >SRAM1

.stack : ALIGN(8) {
. = 16K; /* Overflow causes UsageFault */
} >SRAM2

.sensitive : ALIGN(512) {
*(.sensitive*);
. = ALIGN(512);
} >SRAM2 AT>FLASH

.fb : ALIGN(4) {
__fb_start = .;
*(.fb1*);
*(.fb2*);
__fb_end = .;
. = ALIGN(4);
} >SRAM3

.boot_args : ALIGN(8) {
*(.boot_command*);
. = ALIGN(8);
*(.boot_args*);
. = ALIGN(8);
} >BOOT_ARGS
}
4 changes: 2 additions & 2 deletions core/embed/bootloader/messages.c
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Original file line number Diff line number Diff line change
Expand Up @@ -754,8 +754,8 @@ int process_msg_FirmwareUpload(uint8_t iface_num, uint32_t msg_size,
// write a burst (8 * quadword (16 bytes)) to the flash
ensure(flash_area_write_burst(&FIRMWARE_AREA, write_offset, quadword_ptr),
NULL);
write_offset += 8 * 4 * sizeof(uint32_t);
quadword_ptr += 8 * 4;
write_offset += FLASH_BURST_LENGTH * sizeof(uint32_t);
quadword_ptr += FLASH_BURST_LENGTH;
}
ensure(flash_lock_write(), NULL);

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106 changes: 106 additions & 0 deletions core/embed/bootloader_ci/memory_stm32u58.ld
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Original file line number Diff line number Diff line change
@@ -0,0 +1,106 @@
/* Trezor v2 bootloader linker script */

ENTRY(reset_handler)

MEMORY {
FLASH (rx) : ORIGIN = 0x0C010000, LENGTH = 128K
SRAM1 (wal) : ORIGIN = 0x30000000, LENGTH = 192K - 0x100
BOOT_ARGS (wal) : ORIGIN = 0x3002FF00, LENGTH = 0x100
SRAM2 (wal) : ORIGIN = 0x30030000, LENGTH = 64K
SRAM3 (wal) : ORIGIN = 0x30040000, LENGTH = 512K
SRAM5 (wal) : ORIGIN = 0x30080000, LENGTH = 0K /* SRAM5 is not available */
SRAM6 (wal) : ORIGIN = 0x30080000, LENGTH = 0K /* SRAM6 is not available */
SRAM4 (wal) : ORIGIN = 0x38000000, LENGTH = 16K
}

main_stack_base = ORIGIN(SRAM2) + SIZEOF(.stack); /* 8-byte aligned full descending stack */
_sstack = ORIGIN(SRAM2);
_estack = main_stack_base;

/* used by the startup code to populate variables used by the C code */
data_lma = LOADADDR(.data);
data_vma = ADDR(.data);
data_size = SIZEOF(.data);

/* used by the startup code to populate variables used by the C code */
sensitive_lma = LOADADDR(.sensitive);
sensitive_vma = ADDR(.sensitive);
sensitive_size = SIZEOF(.sensitive);

/* used by the startup code to wipe memory */
sram1_start = ORIGIN(SRAM1);
sram1_end = ORIGIN(SRAM1) + LENGTH(SRAM1);
sram2_start = ORIGIN(SRAM2);
sram2_end = ORIGIN(SRAM2) + LENGTH(SRAM2);
sram3_start = ORIGIN(SRAM3);
sram3_end = ORIGIN(SRAM3) + LENGTH(SRAM3);
sram4_start = ORIGIN(SRAM4);
sram4_end = ORIGIN(SRAM4) + LENGTH(SRAM4);
sram5_start = ORIGIN(SRAM5);
sram5_end = ORIGIN(SRAM5) + LENGTH(SRAM5);
sram6_start = ORIGIN(SRAM6);
sram6_end = ORIGIN(SRAM6) + LENGTH(SRAM6);

/* reserve 256 bytes for bootloader arguments */
boot_args_start = ORIGIN(BOOT_ARGS);
boot_args_end = ORIGIN(BOOT_ARGS) + LENGTH(BOOT_ARGS);

_codelen = SIZEOF(.flash) + SIZEOF(.data) + SIZEOF(.sensitive);

SECTIONS {
.header : ALIGN(4) {
KEEP(*(.header));
} >FLASH AT>FLASH

.flash : ALIGN(512) {
KEEP(*(.vector_table));
. = ALIGN(4);
*(.text*);
. = ALIGN(4);
*(.rodata*);
. = ALIGN(512);
} >FLASH AT>FLASH

.data : ALIGN(4) {
*(.data*);
. = ALIGN(512);
} >SRAM1 AT>FLASH

/DISCARD/ : {
*(.ARM.exidx*);
}

.bss : ALIGN(4) {
*(.bss*);
. = ALIGN(4);
} >SRAM1

.buf : ALIGN(4) {
*(.buf*);
. = ALIGN(4);
} >SRAM1

.stack : ALIGN(8) {
. = 16K; /* Exactly 16K allocated for stack. Overflow causes Usage fault. */
} >SRAM2

.sensitive : ALIGN(512) {
*(.sensitive*);
. = ALIGN(512);
} >SRAM2 AT>FLASH

.fb : ALIGN(4) {
__fb_start = .;
*(.fb1*);
*(.fb2*);
__fb_end = .;
. = ALIGN(4);
} >SRAM3

.boot_args : ALIGN(8) {
*(.boot_command*);
. = ALIGN(8);
*(.boot_args*);
. = ALIGN(8);
} >BOOT_ARGS
}
18 changes: 10 additions & 8 deletions core/embed/firmware/bl_check.c
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Original file line number Diff line number Diff line change
Expand Up @@ -217,25 +217,27 @@ void check_and_replace_bootloader(void) {

do {
uint32_t *p = decomp_out;
uint32_t last_whole_word_addr = (((uint32_t)decomp.dest) & ~3);
uint32_t last_whole_word_addr = (((uint32_t)decomp.dest) & ~0x7F);
while ((uint32_t)p < last_whole_word_addr) {
ensure(flash_area_write_word(&BOOTLOADER_AREA, offset, *p++), NULL);
offset += sizeof(uint32_t);
ensure(flash_area_write_burst(&BOOTLOADER_AREA, offset, p), NULL);
p += FLASH_BURST_LENGTH;
offset += FLASH_BURST_LENGTH * sizeof(uint32_t);
}
if ((uint8_t *)p < decomp.dest) {
// last few bytes in case of unaligned data
uint32_t d = 0;
uint32_t d[FLASH_BURST_LENGTH] = {0};
memcpy(&d, p, (uint32_t)decomp.dest - (uint32_t)p);
ensure(flash_area_write_word(&BOOTLOADER_AREA, offset, d), NULL);
offset += sizeof(uint32_t);
ensure(flash_area_write_burst(&BOOTLOADER_AREA, offset, d), NULL);
offset += FLASH_BURST_LENGTH * sizeof(uint32_t);
}
decomp.dest = (uint8_t *)decomp_out;
} while (uzlib_uncompress(&decomp) >= 0);

uint32_t d[FLASH_BURST_LENGTH] = {0};
// fill the rest of the bootloader area with 0x00
while (offset < bl_len) {
ensure(flash_area_write_word(&BOOTLOADER_AREA, offset, 0x00000000), NULL);
offset += sizeof(uint32_t);
ensure(flash_area_write_burst(&BOOTLOADER_AREA, offset, d), NULL);
offset += FLASH_BURST_LENGTH * sizeof(uint32_t);
}

ensure(flash_lock_write(), NULL);
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