Files regarding synthesis and floorplanning of a RISC-V processor, using Cadence Genus and Innovus. This project is part of the Digital VLSI-ASIC Design course in the 9th semester at the ECE department of Aristotle University.
This project is based on picorv32 Verilog code, which can be found here: YosysHQ/picorv32. Using the above RISC-V CPU and Cadence Genus and Innovus, sythesizing, floorplaning, placing, routing and sign-off are possible.
- Deliverables: Contains the exercise-specific files including constraints, command scripts, and logs.
- Instructions-template files: Contains template files for the project.
- Timing Constraint Files: Contains various timing constraint files (.sdc) used in the project.
This is a University Project and may contain errors!
Class Teacher: Vasileios Pavlidis
Teaching Assistant(responsible for this project): Aristotelis Tsekouras
The Cadence software (Genus, Innovus, Conformal) are kindly provided by Aristotle University of Thessaloniki, and used through the Aristotelis High Performance Cluster, more information for which is available here: Aristotelis HPC