Platform change for STM32U5 only: add I2C and SPI support.

This commit adds the I2C and SPI support that was missing in the previous commit.

Note that ST have acknowledged the problem with the ST-provided CMSIS layer for ThreadX not freeing memory when a dynamic task is terminated: they are looking into a fix, no timescale yet though; this is being progressed in STMicroelectronics/STM32CubeU5#48.

port/api/u_port_i2c.h

@@ -226,11 +226,11 @@ int32_t uPortI2cGetTimeout(int32_t handle);
  * directions; this should be used only on chipsets where the HW
  * interface is limited (e.g. nRF52832, which has a maximum DMA
  * size of 256 for I2C, STM32 on Zephyr which has a similar (though
- * not DMA related) limitation): any transfers above this size will be
- * segmented into N transfers of no more than this size.  If this is
- * not called no segmentation will be applied.  Where this is not
- * supported a weakly-linked function will return
- * #U_ERROR_COMMON_NOT_SUPPORTED.
+ * not DMA related) limitation and STM32U5 on STM32Cube): any
+ * transfers above this size will be segmented into N transfers of
+ * no more than this size.  If this is not called no segmentation will
+ * be applied.  Where this is not supported a weakly-linked function
+ * will return #U_ERROR_COMMON_NOT_SUPPORTED.
  *
  * Note to GNSS users: the receive length of each segment of
  * data from the GNSS device is already limited by

port/platform/common/automation/DATABASE.md

@@ -75,8 +75,8 @@ The table below defines the instances of test hardware available on the `ubxlib`
 | 30    | STM32F407 Discovery, NORA-W3, SARA-R520 EVK|   STM32F4   |             | STM32Cube |            | SARA_R52 M10 NORA_W36            | port device network sock cell ble wifi short_range gnss security mqtt_client http_client location | cell gnss short_range short_range_gen2 | CMSIS_V2 HSE_VALUE=8000000U U_CFG_TEST_GNSS_POWER_SAVING_NOT_SUPPORTED U_CFG_APP_GNSS_UART=-1 U_CFG_LOC_TEST_CHANGE_SYSTEM_TYPES_DISABLE U_CFG_APP_PIN_C030_ENABLE_3V3=-1 U_CFG_APP_PIN_CELL_RESET=-1 U_CFG_APP_CELL_UART=2 U_CFG_APP_PIN_CELL_TXD=0x03 U_CFG_APP_PIN_CELL_RXD=0x02 U_CFG_APP_PIN_CELL_RTS=-1 U_CFG_APP_PIN_CELL_CTS=-1 U_CFG_TEST_PIN_A=-1 U_CFG_TEST_PIN_B=-1 U_CFG_TEST_PIN_C=-1 U_CFG_TEST_UART_A=-1 U_BLE_TEST_CFG_REMOTE_SPS_CENTRAL=2462ABB6CC42p U_BLE_TEST_CFG_REMOTE_SPS_PERIPHERAL=2462ABB6EAC6p U_CFG_APP_SHORT_RANGE_ROLE=3 U_CFG_APP_SHORT_RANGE_UART2=6 U_CFG_APP_PIN_SHORT_RANGE_TXD2=0x26 U_CFG_APP_PIN_SHORT_RANGE_RXD2=0x27 U_DEBUG_UTILS_DUMP_THREADS U_CFG_TEST_GNSS_TRANSPORT_AT_DISABLE |
 | 31    | STM32F7, Nucleo-F767ZI, LARA-R6, live net  |    STM32    | nucleo_f767zi | Zephyr  |            | LARA_R6                          | port device network sock cell security mqtt_client http_client location || U_CFG_TEST_DISABLE_MUX U_CFG_TEST_CELL_PWR_DISABLE U_CELL_TEST_CFG_APN=iot.1nce.net U_CELL_CFG_TEST_USE_FIXED_TIME_SECONDS U_CELL_TEST_NO_INVALID_APN U_CELL_TEST_CFG_BANDMASK1=0x0000000000080084ULL U_CELL_NET_TEST_RAT=U_CELL_NET_RAT_LTE U_CELL_TEST_CFG_MNO_PROFILE=90 U_DEBUG_UTILS_DUMP_THREADS |
 | 32.0  | STM32U5, Nucleo-U575ZI, Zephyr             |    STM32    | nucleo_u575zi_q | Zephyr |           | SARA_U201 M9                     | port device network sock cell security http_client location ubx_protocol gnss spartn || U_CELL_NET_TEST_RAT=U_CELL_NET_RAT_GSM_GPRS_EGPRS U_CELL_TEST_CFG_APN=iot.1nce.net U_CELL_CFG_APN_DEFAULT=iot.1nce.net U_CFG_TEST_TRANSPORT_SECURITY_DISABLE U_CELL_CFG_TEST_USE_FIXED_TIME_SECONDS U_CELL_TEST_NO_INVALID_APN U_CFG_CELL_DISABLE_UART_POWER_SAVING U_CFG_APP_GNSS_I2C=1 U_CFG_APP_I2C_MAX_SEGMENT_SIZE=255 U_GNSS_MGA_TEST_HAS_FLASH U_CFG_TEST_GNSS_POWER_SAVING_NOT_SUPPORTED U_GNSS_MGA_TEST_ASSIST_NOW_AUTONOMOUS_NOT_SUPPORTED U_CFG_TEST_PIN_GNSS_RESET_N=0x5D U_CFG_TEST_UART_A=-1 U_DEBUG_UTILS_DUMP_THREADS |
-| 32.1  | STM32U5, STM32Cube default, Nucleo-U575ZI  |   STM32U5   |             | STM32Cube |            |                                  | port device network sock cell security http_client location ubx_protocol || U_CFG_APP_FILTER=port. U_CELL_NET_TEST_RAT=U_CELL_NET_RAT_GSM_GPRS_EGPRS U_CELL_TEST_CFG_APN=iot.1nce.net U_CELL_CFG_APN_DEFAULT=iot.1nce.net U_CFG_TEST_TRANSPORT_SECURITY_DISABLE U_CELL_CFG_TEST_USE_FIXED_TIME_SECONDS U_CELL_TEST_NO_INVALID_APN U_CFG_CELL_DISABLE_UART_POWER_SAVING U_CFG_APP_GNSS_I2C=-1 U_GNSS_MGA_TEST_HAS_FLASH U_CFG_TEST_GNSS_POWER_SAVING_NOT_SUPPORTED U_GNSS_MGA_TEST_ASSIST_NOW_AUTONOMOUS_NOT_SUPPORTED U_CFG_TEST_PIN_GNSS_RESET_N=0x5D |
-| 32.2  | STM32U5, STM32Cube FreeRTOS, Nucleo-U575ZI |   STM32U5   |             | STM32Cube |  FreeRTOS  | SARA_U201                        | port device network sock cell security http_client location ubx_protocol || U_CELL_NET_TEST_RAT=U_CELL_NET_RAT_GSM_GPRS_EGPRS U_CELL_TEST_CFG_APN=iot.1nce.net U_CELL_CFG_APN_DEFAULT=iot.1nce.net U_CFG_TEST_TRANSPORT_SECURITY_DISABLE U_CELL_CFG_TEST_USE_FIXED_TIME_SECONDS U_CELL_TEST_NO_INVALID_APN U_CFG_CELL_DISABLE_UART_POWER_SAVING U_CFG_APP_GNSS_I2C=-1 U_GNSS_MGA_TEST_HAS_FLASH U_CFG_TEST_GNSS_POWER_SAVING_NOT_SUPPORTED U_GNSS_MGA_TEST_ASSIST_NOW_AUTONOMOUS_NOT_SUPPORTED U_CFG_TEST_PIN_GNSS_RESET_N=0x5D |
+| 32.1  | STM32U5, STM32Cube default, Nucleo-U575ZI  |   STM32U5   |             | STM32Cube |            | SARA_U201 M9                     | port device network sock cell security http_client location ubx_protocol || U_CFG_APP_FILTER=port. U_CELL_NET_TEST_RAT=U_CELL_NET_RAT_GSM_GPRS_EGPRS U_CELL_TEST_CFG_APN=iot.1nce.net U_CELL_CFG_APN_DEFAULT=iot.1nce.net U_CFG_TEST_TRANSPORT_SECURITY_DISABLE U_CELL_CFG_TEST_USE_FIXED_TIME_SECONDS U_CELL_TEST_NO_INVALID_APN U_CFG_CELL_DISABLE_UART_POWER_SAVING U_CFG_APP_GNSS_SPI=-1 U_CFG_APP_GNSS_SPI=-1 U_GNSS_MGA_TEST_HAS_FLASH U_CFG_TEST_GNSS_POWER_SAVING_NOT_SUPPORTED U_GNSS_MGA_TEST_ASSIST_NOW_AUTONOMOUS_NOT_SUPPORTED U_CFG_TEST_PIN_GNSS_RESET_N=0x5D |
+| 32.2  | STM32U5, STM32Cube FreeRTOS, Nucleo-U575ZI |   STM32U5   |             | STM32Cube |  FreeRTOS  | SARA_U201 M9                     | port device network sock cell security http_client location ubx_protocol gnss spartn || U_CELL_NET_TEST_RAT=U_CELL_NET_RAT_GSM_GPRS_EGPRS U_CELL_TEST_CFG_APN=iot.1nce.net U_CELL_CFG_APN_DEFAULT=iot.1nce.net U_CFG_TEST_TRANSPORT_SECURITY_DISABLE U_CELL_CFG_TEST_USE_FIXED_TIME_SECONDS U_CELL_TEST_NO_INVALID_APN U_CFG_CELL_DISABLE_UART_POWER_SAVING U_CFG_APP_GNSS_SPI=-1 U_GNSS_MGA_TEST_HAS_FLASH U_CFG_TEST_GNSS_POWER_SAVING_NOT_SUPPORTED U_GNSS_MGA_TEST_ASSIST_NOW_AUTONOMOUS_NOT_SUPPORTED U_CFG_TEST_PIN_GNSS_RESET_N=0x5D |
 
 Notes:
 - the \#defines listed are *overrides* on the default values that are defined in the code or additional to those defined in the code; they are not a complete list,

port/platform/common/automation/malloc_excludes.txt

@@ -11,6 +11,7 @@ port/u_port_heap.c
 # Platform files that map malloc()/free(), left this way so that customer code can use malloc()/free()
 port/platform/cell_ucpu/r5/src/u_port_clib.c
 port/platform/nrf5sdk/src/heap_useNewlib.c
+port/platform/stm32cube/src/u_port_clib.c
 port/platform/stm32cube/src/heap_useNewlib.c
 port/platform/zephyr/src/u_port_clib.c
 

port/platform/stm32cube/mcu/README.md

@@ -19,10 +19,12 @@ For STM32U5 ST have set the ThreadX system tick to 10 ms; we have aligned the ti
 
 It is a limitation of ThreadX that an item on an RTOS queue has a maximum size of 64 bytes; `ubxlib` is able to work within this constraint.
 
-In the STM32U5 series MCUs, ST have seen the light and implemented 8-byte FIFOs on all UARTs, hence the relatively complex DMA-based UART implementation is not employed for STM32U5.
+In the STM32U5 series MCUs, ST have seen the light and implemented 8-byte FIFOs on all UARTs, hence the relatively complex DMA-based UART implementation used in the STM32F4 port is not employed/required for this STM32U5 port.
 
 STM32U5 supports a single low-power UART; this may be used in `ubxlib` by requesting UART HW block 0 at the [uPortUart](/port/api/u_port_uart.h) API.  It should be noted that the low-power UART is only really low power if the MCU is running from a 32 kHz source clock in which case the maximum UART baud rate is limited to 9600.
 
+The maximum payload size in the I2C HW blocks of the STM32U5 is 255 bytes however this limitation is handled _inside_ the [uPortI2c](/port/api/u_port_i2c.h) API, you do not need to worry about it (i.e. you do NOT need to call `uPortI2cSetMaxSegmentSize()`).
+
 The `ubxlib` code makes no use of the Trust Zone features of the STM32U5; your application may, of course, do so.
 
 For reasons we don't understand, employing code in the target FW to set the SWO rate at boot prevents the NUCLEO-U575ZI-Q board from connecting to a debugger ever again after the board has been power-cycled; only manual intervention (connecting `BOOT0` to `VDD` to boot from ROM, connecting under reset with the [STM32Cube Programmer](https://www.st.com/en/development-tools/stm32cubeprog.html) and performing a full flash erase) recovers the situation.  Since running SWO at the default rate of 2 MHz on the NUCLEO-U575ZI-Q boards doesn't seem to be a problem, use of the SWO-rate-setting code is disabled by default (see `U_CFG_HW_SWO_CLOCK_HZ` in the STM32U5 version of [u_cfg_hw_platform_specific.h](stm32u5/cfg/u_cfg_hw_platform_specific.h)).

port/platform/stm32cube/mcu/stm32u5/cfg/u_cfg_app_platform_specific.h

@@ -214,7 +214,7 @@
  * with a GNSS module.  Note that ST number their HW SPI blocks
  * starting at 1 rather than 0.
  */
-# define U_CFG_APP_GNSS_SPI                  -1
+# define U_CFG_APP_GNSS_SPI                  1
 #endif
 
 /* ----------------------------------------------------------------
@@ -280,28 +280,36 @@
 /** The GPIO output pin for SPI towards the GNSS module;
  * use -1 where there is no such connection.
  */
-# define U_CFG_APP_PIN_GNSS_SPI_MOSI          -1
+# define U_CFG_APP_PIN_GNSS_SPI_MOSI          0x07  // AKA PA_7 or D11 on a NUCLEO-U575ZI-Q board
 #endif
 
 #ifndef U_CFG_APP_PIN_GNSS_SPI_MISO
 /** The GPIO input pin for SPI from the GNSS module;
  * use -1 where there is no such connection.
+ *
+ * Note: the ubxlib test system runs tests on a NUCLEO-U575ZI-Q
+ * board.  In order to test using the LPUART and avoid the application
+ * having to call HAL_PWREx_EnableVddIO2() (since the usual pins
+ * for the LPUART, port G, are not normally powered), it uses
+ * PA_2/PA_3/PA_6/PB_1 for the LPUART pins and, unfortunately
+ * PA_6 is also the MISO pin for SPI1, so here we use PE_14 instead,
+ * which is an alternate (see table 27 of the STM32U575 data sheet).
  */
-# define U_CFG_APP_PIN_GNSS_SPI_MISO          -1
+# define U_CFG_APP_PIN_GNSS_SPI_MISO          0x4e  // AKA PE_14 or D31, labelled "IO2", on a NUCLEO-U575ZI-Q board
 #endif
 
 #ifndef U_CFG_APP_PIN_GNSS_SPI_CLK
 /** The GPIO output pin that is the clock for SPI;
  * use -1 where there is no such connection.
  */
-# define U_CFG_APP_PIN_GNSS_SPI_CLK           -1
+# define U_CFG_APP_PIN_GNSS_SPI_CLK           0x05 // AKA PA_5 or D13 on a NUCLEO-U575ZI-Q board
 #endif
 
 #ifndef U_CFG_APP_PIN_GNSS_SPI_SELECT
 /** The GPIO output pin that is the chip select for the GNSS
  * module; use -1 where there is no such connection.
  */
-# define U_CFG_APP_PIN_GNSS_SPI_SELECT        -1
+# define U_CFG_APP_PIN_GNSS_SPI_SELECT        0x10  // AKA PB_0 or D29, labelled "IO1", on a NUCLEO-U575ZI-Q board
 #endif
 
 /* ----------------------------------------------------------------

port/platform/stm32cube/mcu/stm32u5/stm32u5.mk

@@ -10,4 +10,5 @@ include $(realpath $(MAKEFILE_PATH)/../..)/stm32.mk
 # Add files specific to the STM32U5 way of working
 UBXLIB_SRC += \
 	$(PLATFORM_PATH)/src/u_port_os_pure_cmsis.c \
-	$(PLATFORM_PATH)/src/u_port_clib.c
+	$(PLATFORM_PATH)/src/u_port_clib.c \
+	$(PLATFORM_PATH)/src/i2c_timing_utility.c

port/platform/stm32cube/src/README.md

@@ -33,3 +33,4 @@ These files are relevant only to STM32U5 (for which `U_PORT_STM32_PURE_CMSIS` mu
 - [u_port_clib.c](u_port_clib.c), note: maps `malloc()` and `free()` to ThreadX memory pools, may be ignored if `U_PORT_STM32_CMSIS_ON_FREERTOS` is defined,
 - [sysmem.c](sysmem.c), note: provides an implementation of `_sbrk()` for ThreadX memory pools, may be ignored if `U_PORT_STM32_CMSIS_ON_FREERTOS` is defined,
 - [u_port_os_pure_cmsis.c](u_port_os_pure_cmsis.c), note: a version of [u_port_os.c](u_port_os.c) that adapts only to the CMSIS version 2 API, enabling either ThreadX or FreeRTOS to be used.
+- [i2c_timing_utility.c](i2c_timing_utility.c), note: this file is provided by ST with the I2C examples for STM32U5 as an implementation of the relatively complex calculation required to set the timing register correctly for a given I2C clock rate in Hertz (the I2C HW in the STM32U5 series MCUs is significantly different to that of the STM32F4 series MCUs); it effectively forms part of [u_port_i2c.c](u_port_i2c.c) for STM32U5.