ADD: GPIO is back

src/main/scala/DigitalTop.scala

@@ -21,6 +21,6 @@ class DigitalTop extends BlackBox {
     val uart_0_txd = Output(Bool())
     val uart_0_rxd = Input(Bool())
     val clock_tap = Output(Clock())
-    // val periph_axi4_s_axi = new RawAXI4Lite()
+    val axi4_lite_s_axi = new RawAXI4Lite()
   })
 }

src/main/scala/Elaborate.scala

@@ -83,7 +83,7 @@ object GenerateBitstream extends App {
   )
 
 
-  val chipyard_sources = new File("chipyard/sims/verilator/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral").listFiles(new FileFilter {
+  val chipyard_sources = new File("chipyard/sims/verilator/generated-src/chipyard.harness.TestHarness.WithAXI4LiteTinyRocketConfig/gen-collateral").listFiles(new FileFilter {
     def accept(file: File): Boolean = file.isFile || file.isDirectory
   }).flatMap(file => if (file.isDirectory) file.listFiles().map(_.getAbsolutePath) else Array(file.getAbsolutePath))
   // Exclude files listed in excluded_sources

src/main/scala/TinyRocketArty100T.scala

@@ -37,7 +37,13 @@ class TinyRocketArty100T extends Arty100TShell {
 
 
   val digital_top = Module(new DigitalTop)
-  val udp_core = Module(new udp_core)
+  val udp_core = Module(new udp_core(
+    mac_address = 0x02_00_00_00_00_00L,
+    ip_address = 0x0a_00_00_80,
+    gateway_ip = 0x0a_00_00_01,
+    subnet_mask = 0xff_ff_ff_00,
+    udp_port = 1234
+  ))
 
 
   digital_top.io.auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock := clock
@@ -92,7 +98,7 @@ class TinyRocketArty100T extends Arty100TShell {
   io.led3.g := udp_core.io.led3_g
   io.led3.b := udp_core.io.led3_b
 
-  io.led := Cat(udp_core.io.led7, udp_core.io.led6, udp_core.io.led5, udp_core.io.led4)
+  // io.led := Cat(udp_core.io.led7, udp_core.io.led6, udp_core.io.led5, udp_core.io.led4)
 
   io.jd_3 := false.B
 
@@ -128,4 +134,22 @@ class TinyRocketArty100T extends Arty100TShell {
   udp_core.io.tx_fifo_udp_payload_axis_tlast := udp_payload_axis_fifo.io.m_axis_tlast
   udp_core.io.tx_fifo_udp_payload_axis_tuser := udp_payload_axis_fifo.io.m_axis_tuser
 
+
+  val gpio_0 = Module(new axi_gpio_0)
+  gpio_0.io.s_axi <> digital_top.io.axi4_lite_s_axi
+  gpio_0.io.gpio_io_i := io.btn
+  io.led := gpio_0.io.gpio_io_o
+
+
+
+  // digital_top.io.axi4_lite_s_axi.awready := true.B
+  // digital_top.io.axi4_lite_s_axi.wready := true.B
+  // digital_top.io.axi4_lite_s_axi.bresp := 2.U(2.W)
+  // digital_top.io.axi4_lite_s_axi.bvalid := false.B
+  // digital_top.io.axi4_lite_s_axi.arready := true.B
+  // digital_top.io.axi4_lite_s_axi.rdata := 0.U(32.W)
+  // digital_top.io.axi4_lite_s_axi.rresp := 2.U(2.W)
+  // digital_top.io.axi4_lite_s_axi.rvalid := false.B
+
+
 }

src/main/scala/wrapper/UDPCore.scala

@@ -1,8 +1,21 @@
 import chisel3.{BlackBox, _}
 import chisel3.util._
+import chisel3.experimental.IntParam
 
 
-class udp_core extends BlackBox {
+class udp_core(
+  mac_address: Long = 0x02_00_00_00_00_00L,
+  ip_address: Int = 0xC0_A8_01_80,
+  gateway_ip: Int = 0xC0_A8_01_01,
+  subnet_mask: Int = 0xFF_FF_FF_00,
+  udp_port: Int = 1234
+) extends BlackBox(Map(
+    "MAC_ADDRESS" -> IntParam(mac_address),
+    "IP_ADDRESS" -> IntParam(ip_address),
+    "GATEWAY_IP" -> IntParam(gateway_ip),
+    "SUBNET_MASK" -> IntParam(subnet_mask),
+    "UDP_PORT" -> IntParam(udp_port)
+  )) with HasBlackBoxResource {
   val io = IO(new Bundle {
     val clk = Input(Clock())
     val rst = Input(Reset())

src/main/vsrc/udp_core.v

@@ -33,7 +33,12 @@ THE SOFTWARE.
  */
 module udp_core #
 (
-    parameter TARGET = "XILINX"
+    parameter TARGET = "XILINX",
+    parameter MAC_ADDRESS = 48'h02_00_00_00_00_00,
+    parameter IP_ADDRESS = 32'hC0_A8_01_80,
+    parameter GATEWAY_IP = 32'hC0_A8_01_01,
+    parameter SUBNET_MASK = 32'hFF_FF_FF_00,
+    parameter UDP_PORT = 1234
 )
 (
     /*
@@ -234,10 +239,10 @@ wire tx_udp_payload_axis_tuser;
 // wire tx_fifo_udp_payload_axis_tuser;
 
 // Configuration
-wire [47:0] local_mac   = 48'h02_00_00_00_00_00;
-wire [31:0] local_ip    = {8'd172,  8'd28,   8'd0, 8'd128};
-wire [31:0] gateway_ip  = {8'd172,  8'd28,   8'd0,   8'd1};
-wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255,   8'd0};
+wire [47:0] local_mac   = MAC_ADDRESS;
+wire [31:0] local_ip    = IP_ADDRESS;
+wire [31:0] gateway_ip  = GATEWAY_IP;
+wire [31:0] subnet_mask = SUBNET_MASK;
 
 // IP ports not used
 assign rx_ip_hdr_ready = 1;
@@ -257,7 +262,7 @@ assign tx_ip_payload_axis_tlast = 0;
 assign tx_ip_payload_axis_tuser = 0;
 
 // Loop back UDP
-wire match_cond = rx_udp_dest_port == 1234;
+wire match_cond = rx_udp_dest_port == UDP_PORT;
 wire no_match = !match_cond;
 
 reg match_cond_reg = 0;