UPDATE: match chipyard DigitalTop

ucb-bar · Dec 27, 2024 · a0c5281 · a0c5281
1 parent 5edaa85
commit a0c5281
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Showing 2 changed files with 2 additions and 2 deletions.
diff --git a/src/main/scala/DigitalTop.scala b/src/main/scala/DigitalTop.scala
@@ -21,6 +21,6 @@ class DigitalTop extends BlackBox {
     val uart_0_txd = Output(Bool())
     val uart_0_rxd = Input(Bool())
     val clock_tap = Output(Clock())
-    val axi4_lite_s_axi = new RawAXI4Lite()
+    val periph_axi4_s_axi = new RawAXI4Lite()
   })
 }
diff --git a/src/main/scala/Elaborate.scala b/src/main/scala/Elaborate.scala
@@ -98,7 +98,7 @@ object GenerateBitstream extends App {
   )
 
 
-  val chipyard_sources = new File("chipyard/sims/verilator/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral").listFiles(new FileFilter {
+  val chipyard_sources = new File("chipyard/sims/verilator/generated-src/chipyard.harness.TestHarness.WithPeripheralAXI4LiteTinyRocketConfig/gen-collateral").listFiles(new FileFilter {
     def accept(file: File): Boolean = file.isFile || file.isDirectory
   }).flatMap(file => if (file.isDirectory) file.listFiles().map(_.getAbsolutePath) else Array(file.getAbsolutePath))
   // Exclude files listed in excluded_sources