Skip to content
This repository has been archived by the owner on Sep 25, 2019. It is now read-only.

vaddya/hdl

Folders and files

NameName
Last commit message
Last commit date

Latest commit

author
Vadim Dyachkov
Jan 7, 2019
c1cea69 · Jan 7, 2019

History

76 Commits
Apr 11, 2018
Dec 19, 2017
May 15, 2018
May 15, 2018
Mar 14, 2018
Feb 28, 2018
Dec 19, 2017
May 23, 2018
May 27, 2018
May 29, 2018
Jun 6, 2018
May 15, 2018
May 24, 2018
Jan 7, 2019

Repository files navigation

Hardware Description Languages

  1. Timing Analyzer lab_ta
  2. Design Rules lab_dr
  3. Verilog Hardware Description Language verilog
  4. Metastability Analysis lab_ms
  5. SignalTapII Logic Analyzer lab_la
  6. Contact Bounce Analysis lab_cb
  7. In-System Sources and Probe Editor lab_isspe
  8. In-System Memory Content Editor lab_ismce
  9. ModelSim Simulations modelsim
  10. Qsys & NIOS II nios
  11. Data transmission device transmitter