This repository is a documentation of the 5 day workshop on RTL Design using iverilog and YOSYS for simulation and synthesis with Sky130 PDK. The workshop spanned 5 days from 26th April 2022 to 1 May 2022 with attendees provided remote access to machines with pre installed software and course modules over different topics along with assessments.
First day is about learning what verilog and RTL is, difference between design and synthesis, how they're tied together using testbenches, broad picture of YOSYS, iverilog, Netlists , Cell libraries etc.
Folder verilog_files has all the digital designs in verilog along with testbenches for the trainee to compile and run. Let's see how one uses iverilog to simulate and view waveforms of an upcounter ,called upcntr.v and it's testbench tb_upcntr.v
Use the command ls to view the contents of each directory and navigate to where you cloned the workshop repo.
Use your faviourite text editor to open upcntr.v and tb_upcntr.v , the source and testbench for the upcounter.
nano upcntr.v tb_upcntr.v
Use alt + .to toggle between files.
Behavioural Description
Testbench
Following is the syntax for compiling the upcounter verilog module and it's testbench.
iverilog <module_name.v> <testbench_module_name.v>
Example:
iverilog upcntr.v tb_upcntr.v
The command creates a binary called
a.out
We can specify our own name for the binary using
iverilog -o among_us.out upcntr.v tb_upcntr.v
Let's see what's inside our binary file among_us.out
Execute the binary file created after compiling using
./<binaryfilename>.out
In our case
./among_us.out
The value change dump file will contain the simulation output, let's see what's inside.
nano tb_upcntr.vcd
Open the .vcd file using gtkwave
gtkwave tb_upcntr.vcd
Yosys is an opensource framework for RTL synthesis tools. To realize your HDL in hardware , an important step is to convert that behavioural description of the design to a low level description like a #### Gate Level Netlist ####, which describes the design in terms of standard logic cells like AND, NOR, XOR, FLOPS from a device library.
To syhtesize a gate level netlist, you would need a standard cell library, in our case the sky130 PDK and a verilog module.
Following are the steps to synthesize a verilog module.
Call the yosys tool
yosys
If synthesis is realizing HDL to a gate level netlist, how does one know what gates to use, what parameters for the gates like area, power , delay, number of inputs, outputs, risetime, leakage current and much more. It comes from a .lib file that follows the Liberty syntax ( Library Timing file ) that contains all the information of standard logic cells of a particular technology node with its timing model like setup time, hold time, cell delay , cell transition etc. The .lib file is usually provided by a third party vendor or the foundry itself, if it supports a standard cell library.
Command to import library.
read_liberty -lib <path to .lib file>
In our case
read_liberty -lib ../my_lib/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
Read the verilog module you want to synthesise, lets use the module good_mux.v
read_verilog good_mux.v
Use the synth command to run the default synthesis command on specified verilog module.
synth -top <modulename>
Example
synth -top good_mux
On running synth , the follwoing report is presented by YOSYS.
The ABC pass maps YOSYS's internal gate library to a target architecture, in our case the sky130 lib.
abc [option] [selection]
We use
abc -liberty ../my_lib/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
The report form the pass
Create a graphviz DOT file for the selected part of the design and compile it to a graphics file (usually SVG or PostScript).
Using the command show gives us
A standard cell sky130_fd_sc_hd__mux2_1 is called with ports i0,i1,sel and y mapped suitably.
The sky130 library has different flavours of the same cells , eg - an AND gates basic operation is
A&B
but the liberty file contains several versions of AND gates with varying speed , power usage, rise times, footprint etc - Why ? Because a module made up of a combinatinal block sandwiched between two flops as shown below, needs careful selection of logic cells to meet Hold time and Setup time constraints that when violated will cause glitches or unpredictable states in the system.
Will go in more detail down the line.
We are using devices from the Skywater130nm PDK technology node for constructing our logic cells and the properties of the cells depend on the device parameters too. The cells come in different flavours to optimize application specific needs.
The library name sky130_fd_sc_hd_tt_025C_1v80.lib has the following information encoded in it's name.
fd = foundry, sc = standard cell, hd = high density, tt = typical corner, 025C = 25 degrees Celcius, 1v80 = 1.8 Volts
Different flavours of an and gate for example may have the following specs in terms of leakage power and dimensions among other.
A Hierarchial architecture has submodules inside the verilog program, example multiple_modules.v in verilog_files.
submodule 1 corresponds to an and module and submodule two is a or gate.
Let's see what happens when we synthesize the verilog program
after technology mapping through abc
we run show
