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1. RISCV_MYTH RISCV_MYTH Public

   This repository is a summary of the RISC-V based MYTH workshop organised by VSD and Redwood EDA, made by Ahtesham Ahmed of grade 8.

   TL-Verilog 21 2

2. Spodrue Spodrue Public

   This repository contains a step-by-step guidance to build your own UI called 'Spodrue'.

   Tcl 1

3. pong-game_python pong-game_python Public

   A simple, classic, desktop Pong game 🏓 using Python 🐍,

   Python

4. Calculator_using_tcl Calculator_using_tcl Public

   Tcl

5. rv32im-single-cycle-cpu rv32im-single-cycle-cpu Public

   Verilog-based single-cycle CPU implementing the RV32IM instruction set. Supports integer and multiplication/division instructions with modular design, ALU, control unit, and UART-based debugging.

   Verilog 3 1

6. rv32im-pipelined-cpu rv32im-pipelined-cpu Public

   5-stage pipelined RV32IM core in Verilog.

   Verilog