FPGA DSP Tools (Octave)

This repository provides a small collection of GNU Octave scripts used to generate fixed-point DSP coefficients and lookup tables for FPGA-based audio processing cores.

The focus of this repository is numerical tooling, not DSP cores. All outputs are intended to be consumed directly by RTL designs (FIR, IIR, biquad, non-linear blocks).

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Scope and Philosophy

• Fixed-point first (Q-format based)
• Deterministic and hardware-oriented
• No real-time audio processing
• No floating-point runtime dependency in RTL
• Designed to support AXI-Stream / AXI-Lite based FPGA DSP modules

This repository is meant to support RTL repositories, not replace them.

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Tools Overview

1. FIR Coefficient Generator

File: gen_fir.m

Generates FIR filter coefficients with configurable:

• Number of taps (NTAPS)
• Cutoff frequency (normalized)
• Window function

Filter form:

y[n] = h[0]·x[n] + h[1]·x[n-1] + ... + h[N-1]·x[n-(N-1)]

Output:

• fir_coef.mem (Q1.15, one coefficient per line)
• fir_coef.txt (human-readable)

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2. IIR First-Order Coefficient Generator

File: gen_iir1.m

Implements a standard first-order IIR filter:

y[n] = b0*x[n] + b1*x[n-1] - a1*y[n-1]

Supported types:

• Low-pass
• High-pass

Output format (single file):

b0
b1
a1

Output:

• iir1_coef.mem
• iir1_coef.txt

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3. IIR Biquad Coefficient Generator

File: gen_biquad.m

Standard biquad (Direct Form I):

y[n] = b0·x[n] + b1·x[n-1] + b2·x[n-2] - a1·y[n-1] - a2·y[n-2]

Supported types:

• Low-pass
• High-pass
• Band-pass

Output format:

b0
b1
b2
a1
a2

Output:

• biquad_coef.mem
• biquad_coef.txt

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4. Sine LUT Generator (Verilog Case Statement)

File: sine_gen.m

This script generates a 256-entry sine lookup table (LUT) in the form of a Verilog case statement, suitable for direct inclusion inside RTL modules.

The LUT maps a phase address to a signed sine amplitude.

Key Characteristics

• LUT depth: 256 samples (8-bit phase address)
• Output format: signed 16-bit (Q1.15)
• Full-scale range: ±32767
• Output style: pure combinational case(addr)
• No ROM inference, no $readmemh

This approach is intentionally chosen for:

• Maximum RTL transparency
• Easy inspection and modification
• Small, deterministic waveform generators (LFO, test tone, DDS-style blocks)

Generated Output

• sine_lut_256_body.v

The generated file contains only the body of the LUT logic and is intended to be copy-pasted into a Verilog module, for example:

always @(posedge clk) begin
    case (addr)
        8'd0  : data = 16'h0000;
        8'd1  : data = 16'h0324;
        ...
        default: data = 16'h0000;
    endcase
end

Notes

• Two’s complement conversion is handled explicitly in the script
• Phase range spans 0 → 2π
• Suitable for:
  • Sine oscillators
  • LFOs
  • Test signal generators
  • Non-linear DSP excitation signals
• This tool is not intended for high-precision DDS or large waveform ROMs

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5. Batch CSV Plotter (Offline Visualization Tool)

File: batch_plotter.m

This utility provides a robust, dependency-free batch plotting tool for CSV files generated by simulations, FPGA testbenches, or hardware captures.

It is designed to work reliably on both GNU Octave and MATLAB, including older Octave versions.

Key Characteristics

• No external dependencies
  (no Perl, no table(), no readtable())
• Uses low-level I/O:
  • fopen
  • fgetl
  • dlmread
• Fully offline
• Headless rendering (no GUI required)

Features

• Batch processing of all .csv files in a folder
• Automatic header parsing
• Automatic X-axis detection:
  • Detects monotonic increasing columns (e.g. time, sample index)
  • Falls back to index-based X-axis if none found
• Intelligent grouping of Y-axis signals:
  • _L suffix → Left channel
  • _R suffix → Right channel
  • Others → General
• Automatic grouping based on signal magnitude
  (log-scale friendly)

Each CSV file produces:

• One .png visualization
• Multiple vertically stacked plots if needed

Typical Use Cases

• RTL simulation result inspection
• FPGA audio pipeline debugging
• Comparing left/right channel behavior
• Verifying fixed-point scaling behavior
• Post-processing AXI-stream dumps

Output

For each input file:

• <filename>.png saved in the same directory
• Fully labeled plots
• Legends preserved exactly
  (no interpreter mangling)

Notes

• This tool is not a real-time plotter
• Intended strictly for offline inspection and debugging
• Emphasizes robustness over convenience APIs

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Design Philosophy Reminder

These additional tools follow the same core philosophy as the rest of this repository:

• Deterministic
• Hardware-oriented
• Offline preprocessing / visualization only
• Designed to support RTL-centric FPGA DSP workflows

They are meant to support verification and signal generation, not replace DSP cores or simulation environments.

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Fixed-Point Format

All coefficients are exported in:

• Q1.15 signed fixed-point
• Two’s complement
• Saturated to ±32768

Helper functions:

• q15.m → fixed-point quantization
• write_mem.m → .mem file writer (1 value per line)

The .mem files are directly compatible with:

$readmemh("coef.mem", coef_rom);

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Repository Structure

repo_tools_octave/
│
├── gen_fir.m
├── gen_iir1.m
├── gen_biquad.m
│
├── q15.m
├── write_mem.m
│
└── README.md

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Requirements

• GNU Octave

• Octave package:

  • signal

Load the package explicitly inside scripts:

pkg load signal

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Related FPGA RTL Repositories

The coefficient generators in this repository are designed to be used together with the following FPGA RTL DSP cores:

• IIR 1st-Order Stereo Filter (FPGA)
  https://github.com/vrm-lab/IIR-1st-Order-Stereo-FPGA

• FIR Stereo Filter (FPGA)
  https://github.com/vrm-lab/FIR-Stereo-FPGA

• IIR Biquad Stereo Filter (FPGA)
  https://github.com/vrm-lab/IIR-Biquad-Stereo-FPGA

These RTL repositories consume the .mem coefficient files generated by the Octave scripts in this repository and implement the corresponding filters using fixed-point arithmetic.

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Intended Use

This repository is intended to be used as:

• A coefficient generation toolchain
• A preprocessing step before RTL synthesis
• A companion repository for FPGA DSP cores

It is not intended as:

• A general DSP tutorial
• A floating-point reference implementation
• A real-time audio processing environment

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Notes

• Coefficient ordering is explicit and deterministic
• RTL designs must follow the same coefficient order
• Sign conventions for feedback terms must match RTL implementation

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License

Licensed under the MIT License. Provided as-is, without warranty.