Merge pull request #7 from akukulanski/master

port nmigen -> amaranth

README.md

@@ -1,7 +1,7 @@
 # nMigen-cocotb
 
-nMigen-cocotb is a simple python module which tries to combine
-two amazing HDL tools: nMigen and cocotb
+amaranth-cocotb is a simple python module which tries to combine
+two amazing HDL tools: amaranth (former nMigen) and Cocotb.
 
 # Installation
 

amaranth_cocotb/__init__.py

@@ -0,0 +1 @@
+from .amaranth_cocotb import *

nmigen_cocotb.py → amaranth_cocotb/amaranth_cocotb.py

@@ -1,19 +1,19 @@
-import argparse
 from cocotb_test.simulator import Icarus
-from nmigen import Fragment
-from nmigen.back import verilog
-from nmigen.cli import main_parser, main_runner
-import subprocess
+from amaranth import Fragment
+from amaranth.back import verilog
+from amaranth.cli import main_parser, main_runner
 import tempfile
 import os
 import shutil
 import inspect
 
+
 class Icarus_g2005(Icarus):
     def compile_command(self):
 
         cmd_compile = (
-            ["iverilog", "-o", self.sim_file, "-D", "COCOTB_SIM=1", "-s", self.toplevel, "-g2005"]
+            ["iverilog", "-o", self.sim_file, "-D", "COCOTB_SIM=1", "-s",
+             self.toplevel, "-g2005"]
             + self.get_define_commands(self.defines)
             + self.get_include_commands(self.includes)
             + self.compile_args
@@ -22,6 +22,7 @@ def compile_command(self):
 
         return cmd_compile
 
+
 compile_args_waveforms = ['-s', 'cocotb_waveform_module']
 
 verilog_waveforms = """
@@ -35,16 +36,20 @@ def compile_command(self):
 endmodule
 """
 
+
 def get_current_module():
     module = inspect.getsourcefile(inspect.stack()[1][0])
     return inspect.getmodulename(module)
 
+
 def get_reset_signal(dut, cd):
     return getattr(dut, cd + '_rst')
 
+
 def get_clock_signal(dut, cd):
     return getattr(dut, cd + '_clk')
 
+
 def cocotb_parser():
     parser = main_parser()
     p_action = parser._subparsers._actions[1]
@@ -61,7 +66,9 @@ def cocotb_parser():
         help="clean generated files after simulation")
     return parser
 
-def generate_verilog(verilog_file, design, platform, name='top', ports=(), vcd_file=None):
+
+def generate_verilog(verilog_file, design, platform, name='top',
+                     ports=(), vcd_file=None):
     fragment = Fragment.get(design, platform)
     print(name, ports)
     output = verilog.convert(fragment, name=name, ports=ports)
@@ -72,10 +79,12 @@ def generate_verilog(verilog_file, design, platform, name='top', ports=(), vcd_f
             vcd_file = os.path.abspath(vcd_file)
             f.write(verilog_waveforms.format(vcd_file, name))
 
+
 def copy_extra_files(extra_files, path):
     for f in extra_files:
         shutil.copy(f, path)
 
+
 def dump_file(filename, content, d):
     file_path = d + '/' + filename
     if isinstance(content, bytes):
@@ -91,7 +100,10 @@ def dump_file(filename, content, d):
             f.write(content)
     return file_path
 
-def run(design, module, platform=None, ports=(), name='top', verilog_sources=None, extra_files=None, vcd_file=None, extra_args=None):
+
+def run(design, module, platform=None, ports=(), name='top',
+        verilog_sources=None, extra_files=None, vcd_file=None,
+        simulator=Icarus_g2005, extra_args=None, extra_env=None):
     with tempfile.TemporaryDirectory() as d:
         verilog_file = d + '/nmigen_output.v'
         generate_verilog(verilog_file, design, platform, name, ports, vcd_file)
@@ -111,12 +123,14 @@ def run(design, module, platform=None, ports=(), name='top', verilog_sources=Non
         if extra_args:
             compile_args += extra_args
         os.environ['SIM'] = 'icarus'
-        simulator = Icarus_g2005(toplevel=name,
-                                 module=module,
-                                 verilog_sources=sources,
-                                 compile_args=compile_args,
-                                 sim_build=d)
-        simulator.run()
+        sim = simulator(toplevel=name,
+                        module=module,
+                        verilog_sources=sources,
+                        compile_args=compile_args,
+                        sim_build=d,
+                        extra_env=extra_env)
+        sim.run()
+
 
 def cocotb_runner(parser, args, design, platform=None, name="top", ports=()):
     if args.action == "cocotb":
@@ -129,6 +143,7 @@ def cocotb_runner(parser, args, design, platform=None, name="top", ports=()):
         if args.clean:
             shutil.rmtree('sim_build')
 
+
 def main(*args, **kwargs):
     parser = cocotb_parser()
     parsed_args = parser.parse_args()

example/test.py

@@ -1,17 +1,18 @@
-from nmigen_cocotb import run, get_current_module
+from amaranth_cocotb import run, get_current_module
 from toplevel import design, ports
 
 import cocotb
 from cocotb.triggers import Timer
 
+
 @cocotb.test()
-def just_a_timer(dut):
-    yield Timer(10, 'ns')
+async def just_a_timer(dut):
+    await Timer(10, 'ns')
+
 
 def test_module():
     run(design, get_current_module(), ports=ports, vcd_file='output.vcd')
 
+
 if __name__ == '__main__':
     test_module()
-
-

example/toplevel.py

@@ -1,5 +1,5 @@
-from nmigen import *
-from nmigen_cocotb import main
+from amaranth import Module, Signal
+from amaranth_cocotb import main
 
 design = Module()
 a = Signal()

setup.py

@@ -1,13 +1,13 @@
 from setuptools import setup, find_packages
 
 setup(
-    name="nmigen_cocotb",
-    version="0.1",
+    name='amaranth-cocotb',
     author='Andres Demski',
-    py_modules=['nmigen_cocotb'],
+    packages=find_packages(),
     setup_requires=['cocotb'],
-    install_requires=['cocotb-test @ git+https://github.com/themperek/cocotb-test.git#egg=cocotb-test',
-                      'nmigen @ git+https://github.com/nmigen/nmigen.git@master#egg=nmigen'],
-    #dependency_links=['git+https://github.com/m-labs/nmigen.git#egg=nmigen',
-                      #'git+https://github.com/themperek/cocotb-test.git#egg=cocotb-test']
+    install_requires=[
+        'cocotb-test',
+        'amaranth @ git+https://github.com/amaranth-lang/amaranth.git#egg=amaranth',
+        'amaranth-yosys'
+    ]
 )