RISC-V Simulator

Environment

• Ubuntu 18.04.1 LTS (GNU/Linux 4.15.0-34-generic x86_64)

Prerequisite

• cpp compiler: g++ 7.4.0
• device-tree-compiler: dtc 1.4.5
• riscv-gnu-toolchain

Processor extension implementation

• RV64IMACFD

Compile

$ make

Block diagram

• Introduce all slave on bus

Slave	Base Address	Size	Read&Write	Cacheable
Boot ROM	0x0_0000_0000	32 KB	RO	Y
SRAM0	0x0_0001_0000	64 KB	RW	Y
SRAM1	0x0_0002_0000	64 KB	RW	Y
Cluster	0x0_0004_0000	4 KB	RW	N
Bridge	0x0_1000_0000	256 MB	RW	N
UART	0x0_1000_1000	4 KB	RW	N
HTIF	0x0_1000_2000	4 KB	RW	N
TMDL	0x0_1000_3000	4 KB	RW	N
*CLINT	0x0_1001_0000	64 KB	RW	N
*PLIC	0x0_1400_0000	64 MB	RW	N
DDR0	0x0_2000_0000	8 MB	RW	Y
DDR1	0x0_8000_0000	8 MB	RW	Y
FLASH	0x1_0000_0000	1 GB	RW	Y

• *CLINT: Core-local Interrupt Controller

• *PLIC: Platform Level Interrupt Controller

• You also can modify main/main.cpp to change those configuration

Usage

• We provide prog0~prog13 program that you can run processor
• You can use the following command to simulate

make sim prog=13 # linux simulation

• prog13 is contain bbl, Linux and busybox

• Linux login

  • user name: root
  • password: root
    

• CPU and Linux information
  

Authors

Yu-Tong Shen

tags: RISC-V