High Level Digital Design_

By {Yu Wenlu wy19403@essex.ac.uk University of Essex}

Technologies Used

• Simulation system: Vivado 2021.2
• Target hardware: a Digilent Basys3 board with a Xilinx FPGA: xc7a35tcpg236-1
• Programming languages: VHDL, C

Description

A little taste of using VHDL, Xilinx Vivado software suite and Basys3 design board.

Setup/Installation Requirements

• Clone this repository to your main3_final.
• Navigate to the top level of the directory.
• Open lab project via Vivado
• Burn lab project to Basys3 board

Performance

please click every link below to check lab performance

• assignment1

• • main1

• • main2

• • main3

• lab1

• lab2_2_1

• lab2_2_2

• lab2_2_3

• lab2_3_1

• lab2_4_1

• lab2_4_2

• lab2_5_1