libraries: loader: Bump to 0.53.1 (excluding blobs)

loader/CMakeLists.txt

@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: Apache-2.0
+
+#set(DTC_OVERLAY_FILE ${BOARD}.overlay)
+
+cmake_minimum_required(VERSION 3.20.0)
+
+# get value of NORMALIZED_BOARD_TARGET early
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE} COMPONENTS yaml boards)
+
+set(DTC_OVERLAY_FILE ${CMAKE_CURRENT_LIST_DIR}/../variants/${NORMALIZED_BOARD_TARGET}/${NORMALIZED_BOARD_TARGET}.overlay)
+set(EXTRA_CONF_FILE ${CMAKE_CURRENT_LIST_DIR}/../variants/${NORMALIZED_BOARD_TARGET}/${NORMALIZED_BOARD_TARGET}.conf)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+
+project(app LANGUAGES C CXX)
+
+add_subdirectory(${CMAKE_CURRENT_SOURCE_DIR}/blobs)
+
+# Memory region relocation based on Kconfig
+# Relocate LLEXT heap if region specified
+if(NOT "${CONFIG_LLEXT_HEAP_REGION}" STREQUAL "")
+    zephyr_code_relocate(FILES ${ZEPHYR_BASE}/subsys/llext/llext_mem.c
+                         LOCATION ${CONFIG_LLEXT_HEAP_REGION}_BSS_NOINIT)
+endif()
+
+# Relocate main stack if region specified
+if(NOT "${CONFIG_MAIN_STACK_REGION}" STREQUAL "")
+    zephyr_code_relocate(FILES ${ZEPHYR_BASE}/kernel/init.c
+                         LOCATION ${CONFIG_MAIN_STACK_REGION}_BSS_NOINIT)
+endif()
+
+
+# for USB device stack NEXT
+target_sources_ifdef(CONFIG_USB_DEVICE_STACK_NEXT app PRIVATE
+    ${CMAKE_CURRENT_LIST_DIR}/../cores/arduino/usb_device_descriptor.c
+)
+
+FILE(GLOB app_sources *.c)
+target_sources(app PRIVATE ${app_sources})
+target_compile_definitions(app PUBLIC _XOPEN_SOURCE=700)
+
+target_link_libraries(app PUBLIC blobs)

loader/Kconfig

@@ -0,0 +1,19 @@
+#
+# Copyright (c) 2025 Arduino
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+source "Kconfig.zephyr"
+
+config LLEXT_HEAP_REGION
+	string "LLEXT heap memory region"
+	depends on CODE_DATA_RELOCATION
+	help
+	  Specify the memory region for LLEXT heap.
+
+config MAIN_STACK_REGION
+	string "Main stack memory region"
+	depends on CODE_DATA_RELOCATION
+	help
+	  Specify the memory region for main stack.

loader/blobs/4343WA1_bin_qspi.c

@@ -0,0 +1,20 @@
+/*
+ * Copyright 2025 Arduino SA
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/devicetree.h>
+#include "wiced_resource.h"
+
+#define QUADSPI_MMAP_BASE   DT_REG_ADDR_BY_IDX(DT_NODELABEL(quadspi), 1)
+#define FLASH_CHIP_OFFSET   DT_REG_ADDR(DT_NODELABEL(qspi_flash))
+#define AIROC_PART_OFS      DT_REG_ADDR(DT_NODELABEL(airoc_firmware))
+
+#define FW_ADDR (QUADSPI_MMAP_BASE + FLASH_CHIP_OFFSET + AIROC_PART_OFS)
+#define FW_SIZE 421098 /* same as the _bin.c file */
+
+const resource_hnd_t wifi_firmware_image = {
+	RESOURCE_IN_MEMORY,
+	FW_SIZE,
+	{ .mem = { (const char *) FW_ADDR } }
+};

loader/blobs/CMakeLists.txt

@@ -0,0 +1,18 @@
+zephyr_interface_library_named(blobs)
+
+if (CONFIG_BOARD_ARDUINO_PORTENTA_C33)
+    set(gen_inc_dir ${ZEPHYR_BINARY_DIR}/misc/generated)
+    zephyr_include_directories(${gen_inc_dir})
+    set(gen_dir ${gen_inc_dir}/c33_bl_patch)
+    generate_inc_file_for_target(
+        ${ZEPHYR_CURRENT_LIBRARY}
+        ${CMAKE_CURRENT_SOURCE_DIR}/../../zephyr/blobs/loader/4343WA1_clm_blob.c)/c33_bl.bin
+        ${gen_dir}/c33_bl.bin.inc
+    )
+endif()
+
+if(CONFIG_AIROC_WIFI_CUSTOM)
+    zephyr_include_directories(${CMAKE_CURRENT_SOURCE_DIR}/../../zephyr/blobs/loader/) # for wifi_nvram_image.h
+    zephyr_library_sources(${CMAKE_CURRENT_SOURCE_DIR}/../../zephyr/blobs/loader/4343WA1_clm_blob.c)
+    zephyr_library_sources(4343WA1_bin_qspi.c) # use _bin.c for a static build
+endif()

loader/fixups.c

@@ -0,0 +1,256 @@
+#include <cmsis_core.h>
+#include <zephyr/init.h>
+
+#ifndef CONFIG_CPP
+void __cxa_pure_virtual() {
+	while (1)
+		;
+}
+#endif
+
+int disable_mpu_rasr_xn(void) {
+	uint32_t index;
+	/* Kept the max index as 8(irrespective of soc) because the sram
+	 * would most likely be set at index 2.
+	 */
+	for (index = 0U; index < 8; index++) {
+		MPU->RNR = index;
+#if defined(CONFIG_ARMV8_M_BASELINE) || defined(CONFIG_ARMV8_M_MAINLINE)
+		if (MPU->RBAR & MPU_RBAR_XN_Msk) {
+			MPU->RBAR ^= MPU_RBAR_XN_Msk;
+		}
+#else
+		if (MPU->RASR & MPU_RASR_XN_Msk) {
+			MPU->RASR ^= MPU_RASR_XN_Msk;
+		}
+#endif /* CONFIG_ARMV8_M_BASELINE || CONFIG_ARMV8_M_MAINLINE */
+	}
+	return 0;
+}
+
+#if defined(CONFIG_BOARD_ARDUINO_NANO_33_BLE)
+int disable_bootloader_mpu() {
+	// MPU was previously enabled in the bootloader
+	// https://github.com/bcmi-labs/zephyr/blob/31cb7dd00fd5bce4c69896b3b2ddf6259d0c0f2b/boards/arm/arduino_nano_33_ble/arduino_nano_33_ble_defconfig#L10C1-L10C15
+	__disable_irq();
+	disable_mpu_rasr_xn();
+	__DMB();
+	MPU->CTRL = 0;
+	__enable_irq();
+	return 0;
+}
+
+SYS_INIT(disable_bootloader_mpu, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
+#endif
+
+#if defined(CONFIG_ARM_MPU)
+SYS_INIT(disable_mpu_rasr_xn, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
+#endif
+
+#if defined(CONFIG_SOC_STM32H747XX_M7)
+int enable_bkp_access(void) {
+	/* Enable access to the backup domain */
+	// HAL_PWR_EnableBkUpAccess();
+	SET_BIT(PWR->CR1, PWR_CR1_DBP);
+	return 0;
+}
+
+SYS_INIT(enable_bkp_access, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
+#endif
+
+#if defined(CONFIG_INPUT)
+#include <zephyr/kernel.h>
+#include <zephyr/device.h>
+#include <zephyr/input/input.h>
+typedef void (*zephyr_input_callback_t)(struct input_event *evt, void *user_data);
+
+static zephyr_input_callback_t zephyr_input_cb_func = NULL;
+static void *zephyr_input_cb_data = NULL;
+
+void zephyr_input_register_callback(zephyr_input_callback_t cb, void *user_data) {
+	zephyr_input_cb_func = cb;
+	zephyr_input_cb_data = user_data;
+}
+
+static void zephyr_input_callback(struct input_event *evt, void *user_data) {
+	if (zephyr_input_cb_func) {
+		zephyr_input_cb_func(evt, zephyr_input_cb_data);
+	}
+}
+
+INPUT_CALLBACK_DEFINE(NULL, zephyr_input_callback, NULL);
+#endif
+
+#if defined(CONFIG_BOARD_ARDUINO_GIGA_R1) && defined(CONFIG_VIDEO)
+#include <zephyr/kernel.h>
+#include <zephyr/device.h>
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/logging/log.h>
+
+int camera_ext_clock_enable(void) {
+	int ret;
+	uint32_t rate;
+	const struct device *cam_ext_clk_dev = DEVICE_DT_GET(DT_NODELABEL(pwmclock));
+
+	if (!device_is_ready(cam_ext_clk_dev)) {
+		return -ENODEV;
+	}
+
+	ret = clock_control_on(cam_ext_clk_dev, (clock_control_subsys_t)0);
+	if (ret < 0) {
+		return ret;
+	}
+
+	ret = clock_control_get_rate(cam_ext_clk_dev, (clock_control_subsys_t)0, &rate);
+	if (ret < 0) {
+		return ret;
+	}
+
+	return 0;
+}
+
+SYS_INIT(camera_ext_clock_enable, POST_KERNEL, CONFIG_CLOCK_CONTROL_PWM_INIT_PRIORITY);
+
+#endif
+
+#if defined(CONFIG_SHARED_MULTI_HEAP)
+#include <zephyr/kernel.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/multi_heap/shared_multi_heap.h>
+
+__stm32_sdram1_section static uint8_t __aligned(32) smh_pool[4 * 1024 * 1024];
+
+int smh_init(void) {
+	int ret = 0;
+	ret = shared_multi_heap_pool_init();
+	if (ret != 0) {
+		return ret;
+	}
+
+	struct shared_multi_heap_region smh_sdram = {
+		.addr = (uintptr_t)smh_pool,
+		.size = sizeof(smh_pool),
+		.attr = SMH_REG_ATTR_EXTERNAL,
+	};
+
+	ret = shared_multi_heap_add(&smh_sdram, NULL);
+	if (ret != 0) {
+		return ret;
+	}
+	return 0;
+}
+
+SYS_INIT(smh_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
+#endif
+
+#if defined(CONFIG_BOARD_ARDUINO_PORTENTA_C33) && defined(CONFIG_LLEXT)
+#include <zephyr/kernel.h>
+#include <zephyr/storage/flash_map.h>
+
+int maybe_flash_bootloader(void) {
+	// memcmp the first 256bytes of "embedded bootloader" and address 0x0
+	// if they are different, flash the bootloader
+	const uint8_t embedded_bootloader[] = {
+#include "c33_bl_patch/c33_bl.bin.inc"
+	};
+
+	const struct flash_area *fa;
+	int rc;
+
+	rc = flash_area_open(FIXED_PARTITION_ID(mcuboot), &fa);
+	if (rc) {
+		printk("Failed to open flash area, rc %d\n", rc);
+		return rc;
+	}
+
+	uint8_t flash_bootloader[256];
+	flash_area_read(fa, 0, flash_bootloader, 256);
+
+	if (memcmp(embedded_bootloader, flash_bootloader, 256) != 0) {
+		// flash the bootloader
+		rc = flash_area_erase(fa, 0, fa->fa_size);
+		if (rc) {
+			printk("Failed to erase flash area, rc %d\n", rc);
+			return rc;
+		}
+		flash_area_write(fa, 0, embedded_bootloader, sizeof(embedded_bootloader));
+		if (rc) {
+			printk("Failed to write flash area, rc %d\n", rc);
+			return rc;
+		}
+	}
+	return 0;
+}
+
+SYS_INIT(maybe_flash_bootloader, POST_KERNEL, CONFIG_FILE_SYSTEM_INIT_PRIORITY);
+
+#endif
+
+#if defined(CONFIG_BOARD_ARDUINO_UNO_Q)
+#include "matrix.inc"
+
+#include "../variants/arduino_uno_q_stm32u585xx/variant.h"
+#include <stm32_ll_adc.h>
+#include <zephyr/devicetree.h>
+
+int analog_reference(uint8_t reference) {
+	uint8_t init_status;
+
+	/* VREF+ is connected to VDDA by default */
+	const struct gpio_dt_spec spec =
+		GPIO_DT_SPEC_GET_BY_IDX(DT_PATH(zephyr_user), analog_switch_gpios, 0);
+
+	gpio_pin_configure_dt(&spec, GPIO_OUTPUT);
+
+	__HAL_RCC_SYSCFG_CLK_ENABLE();
+	__HAL_RCC_VREF_CLK_ENABLE();
+
+	HAL_SYSCFG_VREFBUF_HighImpedanceConfig(SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE);
+	HAL_SYSCFG_DisableVREFBUF();
+
+	if (reference == AR_DEFAULT) {
+		/* VREF+ is connected to VDDA */
+		gpio_pin_set_dt(&spec, 0);
+		return 0;
+	}
+
+	gpio_pin_set_dt(&spec, 1);
+
+	if (reference == AR_EXTERNAL) {
+		return 0;
+	}
+
+	uint32_t voltageScaling = SYSCFG_VREFBUF_VOLTAGE_SCALE3;
+	switch (reference) {
+	case AR_INTERNAL2V5:
+		voltageScaling = SYSCFG_VREFBUF_VOLTAGE_SCALE3;
+		break;
+	case AR_INTERNAL2V05:
+		voltageScaling = SYSCFG_VREFBUF_VOLTAGE_SCALE2;
+		break;
+	case AR_INTERNAL1V8:
+		voltageScaling = SYSCFG_VREFBUF_VOLTAGE_SCALE1;
+		break;
+	case AR_INTERNAL1V5:
+		voltageScaling = SYSCFG_VREFBUF_VOLTAGE_SCALE0;
+		break;
+	}
+
+	HAL_SYSCFG_VREFBUF_VoltageScalingConfig(voltageScaling);
+	init_status = HAL_SYSCFG_EnableVREFBUF();
+	HAL_SYSCFG_VREFBUF_HighImpedanceConfig(SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE);
+
+	__ASSERT(init_status == HAL_OK, "ADC Conversion value may be incorrect");
+
+	return init_status;
+}
+
+EXPORT_SYMBOL(analog_reference);
+
+int disable_vrefbuf() {
+	// This is the safe HW configuration
+	return analog_reference(AR_DEFAULT);
+}
+
+SYS_INIT(disable_vrefbuf, POST_KERNEL, 0);
+#endif