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hal: ra: Fix pll clock config get from dts
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The new update of dts in device tree make pll source clock
choose have issue.
We update macro to get the div and freq of pll p q r by
using inforamtion in pll out line

Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
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@duynguyenxa @KhiemNguyenT
duynguyenxa authored and KhiemNguyenT committed Oct 17, 2024
1 parent 6ebe2c4 commit 02b399d
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Showing 3 changed files with 36 additions and 36 deletions.
24 changes: 12 additions & 12 deletions zephyr/ra/ra_cfg/fsp_cfg/bsp/ra8d1/bsp_clock_cfg.h
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Expand Up @@ -40,12 +40,12 @@
#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(0, 0)
#endif

#define BSP_CFG_PLODIVP RA_CGC_CLK_DIV(DT_NODELABEL(pll), divp, 2)
#define BSP_CFG_PLL1P_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), freqp, 0))
#define BSP_CFG_PLODIVQ RA_CGC_CLK_DIV(DT_NODELABEL(pll), divq, 2)
#define BSP_CFG_PLL1Q_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), freqq, 0))
#define BSP_CFG_PLODIVR RA_CGC_CLK_DIV(DT_NODELABEL(pll), divr, 2)
#define BSP_CFG_PLL1R_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), freqr, 0))
#define BSP_CFG_PLODIVP RA_CGC_CLK_DIV(DT_NODELABEL(pllp), div, 2)
#define BSP_CFG_PLL1P_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pllp), freq, 0))
#define BSP_CFG_PLODIVQ RA_CGC_CLK_DIV(DT_NODELABEL(pllq), div, 2)
#define BSP_CFG_PLL1Q_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pllq), freq, 0))
#define BSP_CFG_PLODIVR RA_CGC_CLK_DIV(DT_NODELABEL(pllr), div, 2)
#define BSP_CFG_PLL1R_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pllr), freq, 0))

#define BSP_CFG_PLL2_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pll2)))
#define BSP_CFG_PLL2_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pll2), div, 1)
Expand All @@ -58,12 +58,12 @@
#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL(0, 0)
#endif

#define BSP_CFG_PL2ODIVP RA_CGC_CLK_DIV(DT_NODELABEL(pll2), divp, 2)
#define BSP_CFG_PLL2P_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2), freqp, 0))
#define BSP_CFG_PL2ODIVQ RA_CGC_CLK_DIV(DT_NODELABEL(pll2), divq, 2)
#define BSP_CFG_PLL2Q_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2), freqq, 0))
#define BSP_CFG_PL2ODIVR RA_CGC_CLK_DIV(DT_NODELABEL(pll2), divr, 2)
#define BSP_CFG_PLL2R_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2), freqr, 0))
#define BSP_CFG_PL2ODIVP RA_CGC_CLK_DIV(DT_NODELABEL(pll2p), div, 2)
#define BSP_CFG_PLL2P_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2p), freq, 0))
#define BSP_CFG_PL2ODIVQ RA_CGC_CLK_DIV(DT_NODELABEL(pll2q), div, 2)
#define BSP_CFG_PLL2Q_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2q), freq, 0))
#define BSP_CFG_PL2ODIVR RA_CGC_CLK_DIV(DT_NODELABEL(pll2r), div, 2)
#define BSP_CFG_PLL2R_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2r), freq, 0))

#define BSP_CFG_CLOCK_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pclkblock)))
#define BSP_CFG_CPUCLK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(cpuclk), div, 1)
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24 changes: 12 additions & 12 deletions zephyr/ra/ra_cfg/fsp_cfg/bsp/ra8m1/bsp_clock_cfg.h
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Expand Up @@ -40,12 +40,12 @@
#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(0, 0)
#endif

#define BSP_CFG_PLODIVP RA_CGC_CLK_DIV(DT_NODELABEL(pll), divp, 2)
#define BSP_CFG_PLL1P_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), freqp, 0))
#define BSP_CFG_PLODIVQ RA_CGC_CLK_DIV(DT_NODELABEL(pll), divq, 2)
#define BSP_CFG_PLL1Q_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), freqq, 0))
#define BSP_CFG_PLODIVR RA_CGC_CLK_DIV(DT_NODELABEL(pll), divr, 2)
#define BSP_CFG_PLL1R_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), freqr, 0))
#define BSP_CFG_PLODIVP RA_CGC_CLK_DIV(DT_NODELABEL(pllp), div, 2)
#define BSP_CFG_PLL1P_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pllp), freq, 0))
#define BSP_CFG_PLODIVQ RA_CGC_CLK_DIV(DT_NODELABEL(pllq), div, 2)
#define BSP_CFG_PLL1Q_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pllq), freq, 0))
#define BSP_CFG_PLODIVR RA_CGC_CLK_DIV(DT_NODELABEL(pllr), div, 2)
#define BSP_CFG_PLL1R_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pllr), freq, 0))

#define BSP_CFG_PLL2_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pll2)))
#define BSP_CFG_PLL2_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pll2), div, 1)
Expand All @@ -58,12 +58,12 @@
#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL(0, 0)
#endif

#define BSP_CFG_PL2ODIVP RA_CGC_CLK_DIV(DT_NODELABEL(pll2), divp, 2)
#define BSP_CFG_PLL2P_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2), freqp, 0))
#define BSP_CFG_PL2ODIVQ RA_CGC_CLK_DIV(DT_NODELABEL(pll2), divq, 2)
#define BSP_CFG_PLL2Q_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2), freqq, 0))
#define BSP_CFG_PL2ODIVR RA_CGC_CLK_DIV(DT_NODELABEL(pll2), divr, 2)
#define BSP_CFG_PLL2R_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2), freqr, 0))
#define BSP_CFG_PL2ODIVP RA_CGC_CLK_DIV(DT_NODELABEL(pll2p), div, 2)
#define BSP_CFG_PLL2P_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2p), freq, 0))
#define BSP_CFG_PL2ODIVQ RA_CGC_CLK_DIV(DT_NODELABEL(pll2q), div, 2)
#define BSP_CFG_PLL2Q_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2q), freq, 0))
#define BSP_CFG_PL2ODIVR RA_CGC_CLK_DIV(DT_NODELABEL(pll2r), div, 2)
#define BSP_CFG_PLL2R_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2r), freq, 0))

#define BSP_CFG_CLOCK_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pclkblock)))
#define BSP_CFG_CPUCLK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(cpuclk), div, 1)
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24 changes: 12 additions & 12 deletions zephyr/ra/ra_cfg/fsp_cfg/bsp/ra8t1/bsp_clock_cfg.h
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Original file line number Diff line number Diff line change
Expand Up @@ -39,12 +39,12 @@
#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(0, 0)
#endif

#define BSP_CFG_PLODIVP RA_CGC_CLK_DIV(DT_NODELABEL(pll), divp, 2)
#define BSP_CFG_PLL1P_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), freqp, 0))
#define BSP_CFG_PLODIVQ RA_CGC_CLK_DIV(DT_NODELABEL(pll), divq, 2)
#define BSP_CFG_PLL1Q_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), freqq, 0))
#define BSP_CFG_PLODIVR RA_CGC_CLK_DIV(DT_NODELABEL(pll), divr, 2)
#define BSP_CFG_PLL1R_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), freqr, 0))
#define BSP_CFG_PLODIVP RA_CGC_CLK_DIV(DT_NODELABEL(pllp), div, 2)
#define BSP_CFG_PLL1P_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pllp), freq, 0))
#define BSP_CFG_PLODIVQ RA_CGC_CLK_DIV(DT_NODELABEL(pllq), div, 2)
#define BSP_CFG_PLL1Q_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pllq), freq, 0))
#define BSP_CFG_PLODIVR RA_CGC_CLK_DIV(DT_NODELABEL(pllr), div, 2)
#define BSP_CFG_PLL1R_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pllr), freq, 0))

#define BSP_CFG_PLL2_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pll2)))
#define BSP_CFG_PLL2_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pll2), div, 1)
Expand All @@ -57,12 +57,12 @@
#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(0, 0)
#endif

#define BSP_CFG_PL2ODIVP RA_CGC_CLK_DIV(DT_NODELABEL(pll2), divp, 2)
#define BSP_CFG_PLL2P_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2), freqp, 0))
#define BSP_CFG_PL2ODIVQ RA_CGC_CLK_DIV(DT_NODELABEL(pll2), divq, 2)
#define BSP_CFG_PLL2Q_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2), freqq, 0))
#define BSP_CFG_PL2ODIVR RA_CGC_CLK_DIV(DT_NODELABEL(pll2), divr, 2)
#define BSP_CFG_PLL2R_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2), freqr, 0))
#define BSP_CFG_PL2ODIVP RA_CGC_CLK_DIV(DT_NODELABEL(pll2p), div, 2)
#define BSP_CFG_PLL2P_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2p), freq, 0))
#define BSP_CFG_PL2ODIVQ RA_CGC_CLK_DIV(DT_NODELABEL(pll2q), div, 2)
#define BSP_CFG_PLL2Q_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2q), freq, 0))
#define BSP_CFG_PL2ODIVR RA_CGC_CLK_DIV(DT_NODELABEL(pll2r), div, 2)
#define BSP_CFG_PLL2R_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2r), freq, 0))

#define BSP_CFG_CLOCK_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pclkblock)))
#define BSP_CFG_CPUCLK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(cpuclk), div, 1)
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