boards: Add MCO support for the stm32c0xx family

Add MCO support for the stm32c0xx family. Signed-off-by: Joakim Andersson <joerchan@gmail.com>
zephyrproject-rtos · Aug 28, 2024 · 1afa987 · 1afa987
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diff --git a/dts/arm/st/c0/stm32c0.dtsi b/dts/arm/st/c0/stm32c0.dtsi
@@ -67,6 +67,23 @@
 		};
 	};
 
+	mcos {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		mco1: mco@1 {
+			reg = <0x1>;
+			compatible = "st,stm32-clock-mco";
+			status = "disabled";
+		};
+
+		mco2: mco@2 {
+			reg = <0x2>;
+			compatible = "st,stm32-clock-mco";
+			status = "disabled";
+		};
+	};
+
 	soc {
 		flash: flash-controller@40022000 {
 			compatible = "st,stm32-flash-controller";

diff --git a/include/zephyr/dt-bindings/clock/stm32c0_clock.h b/include/zephyr/dt-bindings/clock/stm32c0_clock.h
@@ -63,6 +63,9 @@
 /** @brief RCC_CSR1 register offset */
 #define CSR1_REG		0x5C
 
+/** @brief CFGR1_REG register offset */
+#define CFGR1_REG               0x08
+
 /** @brief Device domain clocks selection helpers */
 /** CCIPR devices */
 #define USART1_SEL(val)		STM32_CLOCK(val, 3, 0, CCIPR_REG)
@@ -72,4 +75,10 @@
 /** CSR1 devices */
 #define RTC_SEL(val)		STM32_CLOCK(val, 3, 8, CSR1_REG)
 
+/** CFGR1 devices */
+#define MCO1_SEL(val)           STM32_MCO_CFGR(val, 0x7, 24, CFGR1_REG)
+#define MCO1_PRE(val)           STM32_MCO_CFGR(val, 0x7, 28, CFGR1_REG)
+#define MCO2_SEL(val)           STM32_MCO_CFGR(val, 0x7, 16, CFGR1_REG)
+#define MCO2_PRE(val)           STM32_MCO_CFGR(val, 0x7, 20, CFGR1_REG)
+
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32C0_CLOCK_H_ */