spi_nxp_lpspi: Fix faulting control reg access

On some of the platforms, the module doesn't get clocked until the
SDK Init call, causing the control register (CR) write to fault.

The reason for this code in the first place was to avoid S32 chip errata
that caused fifos to need internal logic reset. Since we want to avoid
reconfiguring, and a module reset would require that, there is one other
documented workaround which is to just read the RX fifo register to
update the internal hardware pointer. For the TX fifo the fix is to wait
for transfer completion which should be done by the point of starting a
new one.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>

drivers/spi/spi_nxp_lpspi/spi_nxp_lpspi_common.c

@@ -29,7 +29,9 @@ int spi_mcux_configure(const struct device *dev, const struct spi_config *spi_cf
 	uint32_t clock_freq;
 	int ret;
 
+	/* fast path to avoid reconfigure */
 	if (spi_context_configured(ctx, spi_cfg)) {
+		(volatile uint32_t)base->RDR; /* for ERR050456 */
 		return 0;
 	}
 
@@ -62,16 +64,13 @@ int spi_mcux_configure(const struct device *dev, const struct spi_config *spi_cf
 		return ret;
 	}
 
-	base->CR |= LPSPI_CR_RST_MASK;
-	base->CR |= LPSPI_CR_RRF_MASK | LPSPI_CR_RTF_MASK;
-	base->CR = 0x00U;
-
 	if (data->ctx.config != NULL) {
 		/* Setting the baud rate in LPSPI_MasterInit requires module to be disabled. Only
 		 * disable if already configured, otherwise the clock is not enabled and the
 		 * CR register cannot be written.
 		 */
 		LPSPI_Enable(base, false);
+
 		while ((base->CR & LPSPI_CR_MEN_MASK) != 0U) {
 			/* Wait until LPSPI is disabled. Datasheet:
 			 * After writing 0, MEN (Module Enable) remains set until the LPSPI has