soc: renesas: ra: ra8d1: Disable Dcache as default

Enabling Dcache on RA8D1 will cause many issue with data coherence
in driver.
This commit disable Dcache for RA8D1 as temporary solution, user
can enable it but should be aware of data coherence issue

Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>

soc/renesas/ra/ra8d1/Kconfig.defconfig

@@ -10,7 +10,10 @@ config NUM_IRQS
 config FLASH_FILL_BUFFER_SIZE
 	default 128
 
+config DCACHE
+	default n
+
 config CACHE_MANAGEMENT
-	default y
+	default n
 
 endif # SOC_SERIES_RA8D1

soc/renesas/ra/ra8d1/soc.c

@@ -39,10 +39,12 @@ void soc_early_init_hook(void)
 	SystemCoreClock = BSP_MOCO_HZ;
 	g_protect_pfswe_counter = 0;
 
+#ifdef CONFIG_ICACHE
 	SCB->CCR = (uint32_t)CCR_CACHE_ENABLE;
 	barrier_dsync_fence_full();
 	barrier_isync_fence_full();
-
+#endif
+#if defined(CONFIG_DCACHE) && defined(CONFIG_CACHE_MANAGEMENT)
 	/* Apply Arm Cortex-M85 errata workarounds for D-Cache
 	 * Attributing all cacheable memory as write-through set FORCEWT bit in MSCR register.
 	 * Set bit 16 in ACTLR to 1.
@@ -58,4 +60,5 @@ void soc_early_init_hook(void)
 	barrier_isync_fence_full();
 
 	sys_cache_data_enable();
+#endif
 }