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Benchmark #394
Benchmark #394
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Overall the PR looks good, but I am not convinced we need a new benchmark backend, I think the "counter" backend is enough, but we just need to make it per-core (as you did with the new file, so we could override the old one). The more we have the more maintenance is needed, so let's keep only what we need.
Is "per_code" a typo?
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# A simple configuration to run on StarFive VisionFive 2 platform in release mode |
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We already have multiple VisionFive 2 configs, we need to clarify what this one does and why it is different from the others. It is not obvious from just reading the file for new people coming to the project.
We also need better commit description: "This commit introduces a new benchmark used to debug and understand how the system behaves" does not explain how the new benchmark infrastructure is different and why we needed it. It only states what is obvious from the diff: we have more code now. |
To clarify: it counts per mcause trap reason, not per core. |
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This commit introduces a new benchmark which tracks the number of interrupts for each Mcause exceptions. This benchmark is used only for debugging and doesn't return the values to the kernel when there is an ecall request for measurements. Instead, it simply prints then to UART such that we can analyse the output and have a clearer understanding of the behavior in the system.
Currently, we can only delegate the cycle register in Miralis when delegating the perf counter. This commit adds the two other registers and delegates the perf counters on the VisionFive2 board in the release build.
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Thanks for the changes, looks good :)
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