F23-Omar-Bavly-Architecture
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SingleCycleRV32I
SingleCycleRV32I PublicA single cycle datapath block diagram and Verilog description supporting all of the RV32I instructions except for EBREAK (preventing the program counter from being updated anymore), ECALL and FENCE…
Verilog
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pipelinedRV32
pipelinedRV32 PublicA 5 stage pipelined, single memory implementation of a RV32 CPU. The CPU will support all RV32I base instructions (except for ecall). Stretch goals include: stall on a memory access to avoid struct…
Verilog
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TomasuloSimulator
TomasuloSimulator PublicThe goal of this project is to implement an architectural simulator capable of assessing the performance of a simplified out-of-order 16-bit RISC processor that uses Tomasulo’s algorithm without sp…
C++
Repositories
- TomasuloSimulator Public
The goal of this project is to implement an architectural simulator capable of assessing the performance of a simplified out-of-order 16-bit RISC processor that uses Tomasulo’s algorithm without speculation.
F23-Omar-Bavly-Architecture/TomasuloSimulator’s past year of commit activity - pipelinedRV32 Public
A 5 stage pipelined, single memory implementation of a RV32 CPU. The CPU will support all RV32I base instructions (except for ecall). Stretch goals include: stall on a memory access to avoid structural hazard, support M + C extension, move branch outcome & target address computation to ID stage, and implement 2-bit dynamic branch prediction
F23-Omar-Bavly-Architecture/pipelinedRV32’s past year of commit activity - SingleCycleRV32I Public
A single cycle datapath block diagram and Verilog description supporting all of the RV32I instructions except for EBREAK (preventing the program counter from being updated anymore), ECALL and FENCE instructions will interpreted as no-op instructions that do nothing. 2 separate memories must be used for instructions and memory.
F23-Omar-Bavly-Architecture/SingleCycleRV32I’s past year of commit activity
