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    3 repositories

    • TomasuloSimulator

      Public
      The goal of this project is to implement an architectural simulator capable of assessing the performance of a simplified out-of-order 16-bit RISC processor that uses Tomasulo’s algorithm without speculation.
      C++
      •
      GNU General Public License v2.0
      •0•0•0•0•Updated Dec 12, 2023Dec 12, 2023

    • pipelinedRV32

      Public
      A 5 stage pipelined, single memory implementation of a RV32 CPU. The CPU will support all RV32I base instructions (except for ecall). Stretch goals include: stall on a memory access to avoid structural hazard, support M + C extension, move branch outcome & target address computation to ID stage, and implement 2-bit dynamic branch prediction
      Verilog
      •
      GNU General Public License v3.0
      •0•0•0•0•Updated Nov 26, 2023Nov 26, 2023

    • SingleCycleRV32I

      Public
      A single cycle datapath block diagram and Verilog description supporting all of the RV32I instructions except for EBREAK (preventing the program counter from being updated anymore), ECALL and FENCE instructions will interpreted as no-op instructions that do nothing. 2 separate memories must be used for instructions and memory.
      Verilog
      •
      GNU General Public License v3.0
      •0•0•0•0•Updated Nov 22, 2023Nov 22, 2023