BI-APS semestral

Computer Architecture and Structure

In this project you can find implementation of a simple RISC V processor written in Verilog

Name		Name	Last commit message	Last commit date
Latest commit History 31 Commits
convolution		convolution
semestralka		semestralka
.gitignore		.gitignore
.svlint.toml		.svlint.toml
.svls.toml		.svls.toml
Makefile		Makefile
README.md		README.md
alu.v		alu.v
alu_tb.v		alu_tb.v
controller.v		controller.v
controller_tb.v		controller_tb.v
math.v		math.v
math_tb.v		math_tb.v
mutliplexors.v		mutliplexors.v
mutliplexors_tb.v		mutliplexors_tb.v
register.v		register.v
register_tb.v		register_tb.v
register_utils.v		register_utils.v
test_init.v		test_init.v

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