Update 05_General_Control_Module.md

NYU-Processor-Design · Sep 20, 2023 · 44de965 · 44de965
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diff --git a/Documentation/Module-Docs/05_General_Control_Module.md b/Documentation/Module-Docs/05_General_Control_Module.md
@@ -42,6 +42,7 @@ Note: The inputs and outputs for this module should be made into an interface
   - 32-bit ```MEM_ins``` register
   - 32-bit ```WB_ins``` register
   - 32-bit ```Delayed_ins``` register
+  - 1-bit ```Hazard``` register
 ### On posedge clk