Add(Branch Address Calculator)

* update dv CMakeLists.txt * rtl CMakeLists.txt * dv and rtl * Update Branch_Addr_Calc.sv * Update Branch_Addr_Calc.sv * Update Branch_Addr_Calc.sv * Update Branch_Addr_Calc.sv * Update Branch_Addr_Calc.sv * Update branch_addr_calc.cpp * Update Branch_Addr_Calc.sv * Update Branch_Addr_Calc.sv * Update Branch_Addr_Calc.sv * Update Branch_Addr_Calc.sv * Update Branch_Addr_Calc.sv * Update Branch_Addr_Calc.sv * Update Branch_Addr_Calc.sv * Update Branch_Addr_Calc.sv * Update Branch_Addr_Calc.sv * Update Branch_Addr_Calc.sv * Update Branch_Addr_Calc.sv * Update Branch_Addr_Calc.sv * Update branch_addr_calc.cpp * Update branch_addr_calc.cpp
NYU-Processor-Design · Oct 31, 2023 · 58f99ec · 58f99ec
1 parent 93c11af
commit 58f99ec
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Showing 4 changed files with 149 additions and 3 deletions.
diff --git a/dv/CMakeLists.txt b/dv/CMakeLists.txt
@@ -3,11 +3,11 @@ find_package(nyu-util REQUIRED CONFIG)
 
 add_executable(tests)
 target_sources(tests PRIVATE
-  alu.cpp branch_eval.cpp pc.cpp ifid.cpp memwb.cpp gpr.cpp exmem.cpp
+  alu.cpp branch_eval.cpp pc.cpp ifid.cpp memwb.cpp gpr.cpp exmem.cpp branch_addr_calc.cpp
 )
 nyu_link_sv(tests PRIVATE core)
 nyu_target_verilate(tests
-  TOP_MODULES Alu Branch_Eval PC IFID MEMWB GPR EXMEM
+  TOP_MODULES Alu Branch_Eval PC IFID MEMWB GPR EXMEM Branch_Addr_Calc
   ARGS COVERAGE
 )
 target_link_libraries(tests PRIVATE Catch2::Catch2WithMain nyu::covrecorder)

diff --git a/dv/branch_addr_calc.cpp b/dv/branch_addr_calc.cpp
@@ -0,0 +1,102 @@
+#include <catch2/catch_test_macros.hpp>
+#include <VBranch_Addr_Calc.h>
+#include <cstdint>
+#include <stdlib.h>  
+#include <math.h>
+
+TEST_CASE("PC No Branch") {  //Case when branch_addr = pc + imm, but branch is not taken
+    VBranch_Addr_Calc model;
+    bool mode;
+    bool taken;
+    uint32_t imm;
+    uint32_t rs1d;
+    uint32_t pc_in;
+
+    for (int i = 0; i < 1000; i++) {
+        imm = rand() % (int) (pow(2, 32) - 1);
+        rs1d = rand() % (int) (pow(2, 32) - 1);
+        mode = 0;
+        taken = 0;
+
+        model.addr_mode = mode;
+        model.imm = imm;
+        model.rs1d = rs1d;
+        model.branch_taken = taken;
+        model.eval();
+        REQUIRE((uint32_t) model.branch_addr == (uint32_t) (model.pc_in + model.imm));
+        REQUIRE((uint32_t) model.npc == (uint32_t) model.pc_in);
+    }
+}
+
+TEST_CASE("PC Branch") { //Case when branch_addr = pc + imm, and branch is taken
+    VBranch_Addr_Calc model;
+    bool mode;
+    bool taken;
+    uint32_t imm;
+    uint32_t rs1d;
+    uint32_t pc_in;
+
+    for (int i = 0; i < 1000; i++) {
+        imm = rand() % (int) (pow(2, 32) - 1);
+        rs1d = rand() % (int) (pow(2, 32) - 1);
+        mode = 0;
+        taken = 1;
+
+        model.addr_mode = mode;
+        model.imm = imm;
+        model.rs1d = rs1d;
+        model.branch_taken = taken;
+        model.eval();
+        REQUIRE((uint32_t) model.branch_addr == (uint32_t) (model.pc_in + model.imm));
+        REQUIRE((uint32_t) model.npc == (uint32_t) model.branch_addr);
+    }
+}
+
+
+TEST_CASE("RS1D No Branch") { //Case when branch_addr = imm + rs1d, but branch is not taken
+    VBranch_Addr_Calc model;
+    bool mode;
+    bool taken;
+    uint32_t imm;
+    uint32_t rs1d;
+    uint32_t pc_in;
+
+    for (int i = 0; i < 1000; i++) {
+        imm = rand() % (int) (pow(2, 32) - 1);
+        rs1d = rand() % (int) (pow(2, 32) - 1);
+        mode = 1;
+        taken = 0;
+
+        model.addr_mode = mode;
+        model.imm = imm;
+        model.rs1d = rs1d;
+        model.branch_taken = taken;
+        model.eval();
+        REQUIRE((uint32_t) model.branch_addr == (uint32_t) (model.imm + model.rs1d));
+        REQUIRE((uint32_t) model.npc == (uint32_t) model.pc_in);
+    }
+}
+
+TEST_CASE("RS1D Branch") { //Case when branch_addr = rs1d, and branch is taken
+    VBranch_Addr_Calc model;
+    bool mode;
+    bool taken;
+    uint32_t imm;
+    uint32_t rs1d;
+    uint32_t pc_in;
+
+    for (int i = 0; i < 1000; i++) {
+        imm = rand() % (int) (pow(2, 32) - 1);
+        rs1d = rand() % (int) (pow(2, 32) - 1);
+        mode = 1;
+        taken = 1;
+
+        model.addr_mode = mode;
+        model.imm = imm;
+        model.rs1d = rs1d;
+        model.branch_taken = taken;
+        model.eval();
+        REQUIRE((uint32_t) model.branch_addr == (uint32_t) (model.imm + model.rs1d));
+        REQUIRE((uint32_t) model.npc == (uint32_t) model.branch_addr);
+    }
+}
diff --git a/rtl/Branch_Addr_Calc.sv b/rtl/Branch_Addr_Calc.sv
@@ -0,0 +1,44 @@
+//Branch Address Conditions
+parameter PC = 0;   //Case when branch_addr = pc + imm
+parameter RD = 1;   //Case when branch_addr = imm + rs1d
+
+module Branch_Addr_Calc # (
+    WordSize = 32
+)(
+    input addr_mode, branch_taken,
+    input [WordSize - 1:0] imm, rs1d, pc_in,
+    output logic [WordSize - 1:0] branch_addr, npc
+);
+
+always_comb begin
+    case(addr_mode)
+        PC:
+            case (branch_taken)
+                1'b0: begin
+                    branch_addr = pc_in + imm;
+                    npc = pc_in;
+                end
+                1'b1: begin
+                    branch_addr = pc_in + imm;
+                    npc = branch_addr; 
+                end 
+            endcase
+        RD:
+            case (branch_taken)
+                1'b0: begin
+                    branch_addr = imm + rs1d;
+                    npc = pc_in;
+                end
+                1'b1: begin
+                    branch_addr = imm + rs1d;
+                    npc = branch_addr;
+                end
+            endcase
+        default: begin
+            branch_addr = pc_in + imm;
+            npc = pc_in;
+        end
+    endcase
+end
+
+endmodule
diff --git a/rtl/CMakeLists.txt b/rtl/CMakeLists.txt
@@ -1,3 +1,3 @@
 nyu_add_sv(core
-  Alu.sv Branch_Eval.sv PC.sv IFID.sv MEMWB.sv GPR.sv EXMEM.sv
+  Alu.sv Branch_Eval.sv PC.sv IFID.sv MEMWB.sv GPR.sv EXMEM.sv Branch_Addr_Calc.sv
 )