update docs(10_L1_Data_Cache.md, 03_L1_Data_Cache.md), rtl(L1_Data_Ca…

…che.sv), dv(sVerilogTests)

Documentation/01_Module_Docs/10_L1_Data_Cache.md

@@ -1,41 +1,72 @@
-# THIS MODULE IS NOT YET OUTLINED #
-
-# L1 Data Cache #
-(Any Notes would go here)
-
-## Contents
-* [Inputs](#inputs)
-* [Outputs](#outputs)
-* [Functionality](#functionality)
-  * [Registers](#registers)
-  * [Clk](#on-posedge-clk)
-  * [Active low reset](#asynchronous-active-low-reset)
-
-## Inputs
-|Name|Bits wide|
-|:---|:---:|
-|```name```|#-bit|
-|```name```|#-bit|
-
-## Outputs
-|Name|Bits wide|
-|:---|:---:|
-|```name```|#-bit|
-|```name```|#-bit|
+# L1_Data_Cache Module
+
+## Overview
+`L1_Data_Cache` is a Verilog module designed to simulate an L1 data cache with a write-back policy and a least recently used (LRU) replacement algorithm. This module is a part of a larger memory hierarchy system and interacts with lower memory levels (like L2 cache).
+
+## Module Interface
+
+### Inputs
+- **clk**: Clock signal.
+- **reset**: Reset signal.
+- **write_enable**: Enable signal for write operations.
+- **read_enable**: Enable signal for read operations.
+- **request_address**: Address for the current read/write request.
+- **write_data**: Data to be written into the cache.
+- **l2_response_data**: Data received from the L2 cache.
+- **l2_ready**: Signal indicating readiness of the L2 cache.
+
+### Outputs
+- **response_data**: Data returned in response to a read operation.
+- **c_state**: Current state of the cache (for debugging/monitoring).
+- **l2_request**: Signal to request data from L2 cache.
+- **l2_write_enable**: Enable signal for writing data to L2 cache.
+- **l2_address**: Address for L2 cache operations.
+- **l2_write_data**: Data to be written to the L2 cache.
+
+## Key Parameters and Constants
+- **CACHE_SIZE**: Total size of the L1 cache (4 KB).
+- **BLOCK_SIZE**: Size of each cache block (4 bytes).
+- **ASSOCIATIVITY**: Set associativity of the cache (2-way).
+- **DATA_WIDTH**: Width of the data (32 bits).
+- **NUM_SETS**: Number of sets in the cache.
+- **ADDR_WIDTH**: Width of the memory address.
+
+## Internal Design
+
+### SRAM Module
+- The cache utilizes an `sram_module` for storing and retrieving cache data.
+
+### Cache Structure
+- The cache is organized into sets and ways, with arrays for tags, valid bits, and dirty bits.
+- LRU counters are maintained for each set to implement the LRU replacement policy.
+
+### State Machine
+- The cache operates as a `Mealy`` finite state machine with states: `IDLE`, `CHECK_TAG`, `WRITEBACK`, and `FILL`.
 
 ## Functionality
-### Registers
-  - #-bit ```name``` register
-  - #-bit ```name``` register
-### On posedge clk
-  - ```somebranch = someval```
-  - Use a table when necessary if statements are used:
-  - ```name```
-    |Name|Bits wide|
-    |---|---|
-    |```name == 0```|```reg = val```|
-    |```name == 1```|```reg = val```|
-
-
-### Asynchronous active low reset
-  - Register values reset to 0
+
+### Cache Operations
+- **Read/Write Access**: On receiving a read or write request, the cache checks for a hit or miss.
+- **Write-Back**: On a write miss with a dirty line, data is written back to the lower memory level.
+- **Cache Fill**: On a miss, data is loaded from the lower memory level.
+
+### LRU Algorithm
+- The cache uses an LRU algorithm to determine which cache line to replace on a miss.
+
+### Reset Logic
+- A reset functionality is provided to clear the cache and reset its state.
+
+## Implementation Details
+
+### Tasks and Functions
+- Several tasks and functions are used to modularize operations like handling cache hits, cache misses, LRU calculations, and SRAM interactions.
+
+### Handling Cache States
+- The module defines specific tasks for handling different cache states and transitioning between them based on the current operation.
+
+## Notes & Scope for Improvements
+- This module is designed with considerations for modularity and performance optimization. It can be integrated into larger systems requiring cache functionality with LRU management.
+- ECC, byte accessible, Non-blocking cache, different controllers 
+
+
+---

Documentation/02_Complex_Module_Functions/03_L1_Data_Cache.md

@@ -1 +1,83 @@
-(Note: This document is currently incomplete)
+# L1_Data_Cache Module Detailed Documentation
+
+## Overview
+The `L1_Data_Cache` module in Verilog simulates an L1 data cache with write-back policy and LRU (Least Recently Used) replacement strategy. It's designed to interface with an L2 cache in a memory hierarchy.
+
+## Module Structure
+
+### Inputs and Outputs
+
+#### Inputs
+| Input             | Description                           | Bit Width |
+|-------------------|---------------------------------------|-----------|
+| `clk`             | Clock signal                          | 1         |
+| `reset`           | Reset signal                          | 1         |
+| `write_enable`    | Enable signal for write operations    | 1         |
+| `read_enable`     | Enable signal for read operations     | 1         |
+| `request_address` | Address for read/write request        | 32        |
+| `write_data`      | Data to write into cache              | 32        |
+| `l2_response_data`| Data received from L2 cache           | 32        |
+| `l2_ready`        | Signal indicating L2 cache readiness  | 1         |
+
+#### Outputs
+| Output            | Description                           | Bit Width |
+|-------------------|---------------------------------------|-----------|
+| `response_data`   | Data output for read operations       | 32        |
+| `c_state`         | Current state of cache (debugging)    | 2         |
+| `l2_request`      | Request signal for L2 cache           | 1         |
+| `l2_write_enable` | Write enable for L2 cache             | 1         |
+| `l2_address`      | Address for L2 cache operations       | 32        |
+| `l2_write_data`   | Data to write to L2 cache             | 32        |
+
+### Parameters and Constants
+
+| Parameter         | Description                         | Value / Formula                |
+|-------------------|-------------------------------------|--------------------------------|
+| `CACHE_SIZE`      | Total size of L1 cache              | 4 * 1024 (4 KB)                |
+| `BLOCK_SIZE`      | Size of each cache block            | 4 bytes                        |
+| `ASSOCIATIVITY`   | Set associativity of cache          | 2-way                          |
+| `DATA_WIDTH`      | Width of data                       | 32 bits                        |
+| `BLOCK_WIDTH`     | Width of each cache block           | `BLOCK_SIZE * 8`               |
+| `NUM_SETS`        | Number of sets in cache             | `CACHE_SIZE / (BLOCK_SIZE * ASSOCIATIVITY)` |
+| `ADDR_WIDTH`      | Width of memory address             | 32 bits                        |
+| `OFFSET_WIDTH`    | Width of block offset               | Calculated from `BLOCK_SIZE`   |
+| `INDEX_WIDTH`     | Width of cache set index            | Calculated from `NUM_SETS`     |
+| `TAG_WIDTH`       | Width of cache tag                  | `ADDR_WIDTH - OFFSET_WIDTH - INDEX_WIDTH` |
+
+### Cache Structure
+
+| Component         | Description                       | Type / Bit Width                |
+|-------------------|-----------------------------------|---------------------------------|
+| `cache_tags`      | Stores tags for each cache line   | Array of TAG_WIDTH              |
+| `valid`           | Indicates if a cache line is valid| Array of 1-bit flags            |
+| `dirty`           | Indicates if a cache line is dirty| Array of 1-bit flags            |
+| `lru_counter`     | LRU counters for each cache line  | Array of counters               |
+
+## Functional Overview
+
+### State Machine
+The cache operates through a state machine with distinct states for handling various operations:
+- **IDLE**: Awaiting read or write requests.
+- **CHECK_TAG**: Checking if the requested address is in the cache (cache hit) or not (cache miss).
+- **WRITEBACK**: Writing back data to the L2 cache for dirty cache lines on a miss.
+- **FILL**: Fetching data from the L2 cache to fill the cache line on a miss.
+
+### Cache Operations
+- **Read/Write**: Handles read and write operations, checking for cache hits or misses.
+- **Write-Back**: Writes back dirty data to L2 cache on misses.
+- **Cache Fill**: Loads data from L2 cache on misses.
+
+### LRU Algorithm
+- Implements an LRU algorithm for cache line replacement.
+
+### Modular Design
+- The module leverages tasks and functions to compartmentalize operations such as hit/miss handling, LRU logic, and SRAM interactions.
+
+### State Handling
+- Dedicated tasks manage state transitions and actions, ensuring clear and maintainable state logic.
+
+## Integration and Performance
+- The design is optimized for integration into systems requiring L1 cache functionality, with a focus on performance and modularity.
+
+
+---