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refactor: Formatting and syntax fixes
Build: * Update vcpkg bootstrapping to new style * Inline vcpkg-configuration.json * Update baselines Style: * Reformat all system verilog files with verible-format * " or " -> ", " Function: * Fix all verilog-style always blocks -> SV-style always_ff blocks * Fix all blocking assignments in non-blocking contexts * Fix a couple missing semi-colons * Normalize all port lists, necessary for some synthesizers (Quartus) Refactor: * Significantly simplify Alu.sv, don't try to out-smart the synthesizer * Avoid unnecessary clock-gate latch in Branch_Manager.sv
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@@ -1,44 +1,48 @@ | ||
//Branch Address Conditions | ||
parameter PC = 0; //Case when branch_addr = pc + imm | ||
parameter RD = 1; //Case when branch_addr = imm + rs1d | ||
parameter PC = 0; //Case when branch_addr = pc + imm | ||
parameter RD = 1; //Case when branch_addr = imm + rs1d | ||
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module Branch_Addr_Calc # ( | ||
module Branch_Addr_Calc #( | ||
WordSize = 32 | ||
)( | ||
input addr_mode, branch_taken, | ||
input [WordSize - 1:0] imm, rs1d, pc_in, | ||
output logic [WordSize - 1:0] branch_addr, npc | ||
) ( | ||
input addr_mode, | ||
input branch_taken, | ||
input [WordSize - 1:0] imm, | ||
input [WordSize - 1:0] rs1d, | ||
input [WordSize - 1:0] pc_in, | ||
output logic [WordSize - 1:0] branch_addr, | ||
output logic [WordSize - 1:0] npc | ||
); | ||
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always_comb begin | ||
case(addr_mode) | ||
PC: | ||
case (branch_taken) | ||
1'b0: begin | ||
branch_addr = pc_in + imm; | ||
npc = pc_in; | ||
end | ||
1'b1: begin | ||
branch_addr = pc_in + imm; | ||
npc = branch_addr; | ||
end | ||
endcase | ||
RD: | ||
case (branch_taken) | ||
1'b0: begin | ||
branch_addr = imm + rs1d; | ||
npc = pc_in; | ||
end | ||
1'b1: begin | ||
branch_addr = imm + rs1d; | ||
npc = branch_addr; | ||
end | ||
endcase | ||
default: begin | ||
branch_addr = pc_in + imm; | ||
npc = pc_in; | ||
always_comb begin | ||
case (addr_mode) | ||
PC: | ||
case (branch_taken) | ||
1'b0: begin | ||
branch_addr = pc_in + imm; | ||
npc = pc_in; | ||
end | ||
1'b1: begin | ||
branch_addr = pc_in + imm; | ||
npc = branch_addr; | ||
end | ||
endcase | ||
RD: | ||
case (branch_taken) | ||
1'b0: begin | ||
branch_addr = imm + rs1d; | ||
npc = pc_in; | ||
end | ||
1'b1: begin | ||
branch_addr = imm + rs1d; | ||
npc = branch_addr; | ||
end | ||
endcase | ||
default: begin | ||
branch_addr = pc_in + imm; | ||
npc = pc_in; | ||
end | ||
endcase | ||
end | ||
end | ||
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endmodule | ||
endmodule |
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@@ -1,28 +1,28 @@ | ||
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//Branch condition definitions | ||
parameter NE = 2'h0; //Non branching instruction | ||
parameter ALU = 2'h1; //Branch condition is < or != | ||
parameter NALU = 2'h2; //Branch condition is >= or = | ||
parameter AL = 2'h3; //Jump instruction | ||
parameter NE = 2'h0; //Non branching instruction | ||
parameter ALU = 2'h1; //Branch condition is < or != | ||
parameter NALU = 2'h2; //Branch condition is >= or = | ||
parameter AL = 2'h3; //Jump instruction | ||
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module Branch_Eval #( | ||
WordSize = 32 | ||
)( | ||
WordSize = 32 | ||
) ( | ||
input [WordSize - 1:0] alu_out, | ||
input [1:0] branch_cond, | ||
output logic act_taken | ||
); | ||
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always_comb begin | ||
case(branch_cond) | ||
NE: act_taken = 0; | ||
ALU: act_taken = |alu_out; | ||
NALU: act_taken = ~(|alu_out); | ||
AL: act_taken = 1; | ||
always_comb begin | ||
case (branch_cond) | ||
NE: act_taken = 0; | ||
ALU: act_taken = |alu_out; | ||
NALU: act_taken = ~(|alu_out); | ||
AL: act_taken = 1; | ||
endcase | ||
end | ||
end | ||
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endmodule |
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@@ -1,36 +1,39 @@ | ||
module Branch_Manager #( | ||
WordSize = 32 | ||
)( | ||
input clk, rstn, pred_taken, act_taken, | ||
input [WordSize - 1:0] pred_pc, pred_addr, | ||
WordSize = 32 | ||
) ( | ||
input clk, | ||
input rstn, | ||
input pred_taken, | ||
input act_taken, | ||
input [WordSize - 1:0] pred_pc, | ||
input [WordSize - 1:0] pred_addr, | ||
output logic flush, | ||
output logic [WordSize - 1:0] npc | ||
); | ||
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logic restart; | ||
logic restart; | ||
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always @ (posedge clk or negedge rstn) begin | ||
always_ff @(posedge clk or negedge rstn) begin | ||
if (!rstn) begin | ||
restart <= 1; | ||
flush <= 0; | ||
npc <= 0; | ||
end | ||
else begin | ||
end else begin | ||
restart <= 0; | ||
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if ((pred_taken != act_taken) && !restart) begin | ||
flush <= 1; | ||
case(act_taken) | ||
0: npc <= pred_pc + 4; | ||
1: npc <= pred_addr; | ||
case (act_taken) | ||
0: npc <= pred_pc + 4; | ||
1: npc <= pred_addr; | ||
endcase | ||
end | ||
else begin | ||
end else begin | ||
flush <= 0; | ||
case(pred_taken) | ||
0: npc <= pred_pc + 4; | ||
1: npc <= pred_addr; | ||
case (pred_taken) | ||
0: npc <= pred_pc + 4; | ||
1: npc <= pred_addr; | ||
endcase | ||
end | ||
if (restart) restart <= 0; | ||
end | ||
end | ||
endmodule | ||
end | ||
endmodule |
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Original file line number | Diff line number | Diff line change |
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@@ -1,38 +1,40 @@ | ||
module Branch_Predictor ( | ||
input clk, rstn_h, act_taken, pred_taken, | ||
input [1:0] branch_occr, branch_cond, | ||
input clk, | ||
input rstn_h, | ||
input act_taken, | ||
input pred_taken, | ||
input [1:0] branch_occr, | ||
input [1:0] branch_cond, | ||
output logic branch_taken | ||
); | ||
logic curr_pred, incorrect_pred; | ||
logic curr_pred, incorrect_pred; | ||
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always @ (posedge clk or negedge rstn_h) begin | ||
always_ff @(posedge clk or negedge rstn_h) begin | ||
if (!rstn_h) begin | ||
curr_pred <= 0; | ||
incorrect_pred <= 0; | ||
end | ||
else begin | ||
end else begin | ||
if (^branch_cond == 0) begin | ||
curr_pred <= curr_pred; | ||
incorrect_pred <= incorrect_pred; | ||
end | ||
else if (act_taken ^ pred_taken == 0) begin | ||
end else if (act_taken ^ pred_taken == 0) begin | ||
curr_pred <= curr_pred; | ||
incorrect_pred <= 0; | ||
end | ||
else if (incorrect_pred) begin | ||
end else if (incorrect_pred) begin | ||
curr_pred <= ~curr_pred; | ||
incorrect_pred <= 1; | ||
end | ||
else begin | ||
end else begin | ||
curr_pred <= curr_pred; | ||
incorrect_pred <= 1; | ||
end | ||
end | ||
end | ||
always_comb begin | ||
case(branch_occr[1]) | ||
0: branch_taken = branch_occr[0]; | ||
1: branch_taken = curr_pred; | ||
end | ||
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always_comb begin | ||
case (branch_occr[1]) | ||
0: branch_taken = branch_occr[0]; | ||
1: branch_taken = curr_pred; | ||
endcase | ||
end | ||
end | ||
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endmodule |
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@@ -1,20 +1,54 @@ | ||
module Con_EX #( | ||
WordSize = 32 | ||
)( | ||
input clk, rstn, branch_taken_in, | ||
input[1:0] a_sel, b_sel, | ||
input[WordSize - 1:0] imm, pc_in, rs1d, rs2d_in, branch_addr_in, | ||
input[4:0] rdn_in, | ||
input[5:0] alu_mode, | ||
output logic branch_taken, | ||
output logic [4:0] rdn, | ||
output logic [WordSize - 1:0] pc, branch_addr, rs2d, alu_out | ||
WordSize = 32 | ||
) ( | ||
input clk, | ||
input rstn, | ||
input branch_taken_in, | ||
input [1:0] a_sel, | ||
input [1:0] b_sel, | ||
input [WordSize - 1:0] imm, | ||
input [WordSize - 1:0] pc_in, | ||
input [WordSize - 1:0] rs1d, | ||
input [WordSize - 1:0] rs2d_in, | ||
input [WordSize - 1:0] branch_addr_in, | ||
input [4:0] rdn_in, | ||
input [5:0] alu_mode, | ||
output logic branch_taken, | ||
output logic [4:0] rdn, | ||
output logic [WordSize - 1:0] pc, | ||
output logic [WordSize - 1:0] branch_addr, | ||
output logic [WordSize - 1:0] rs2d, | ||
output logic [WordSize - 1:0] alu_out | ||
); | ||
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logic [WordSize - 1:0] a, b; | ||
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IDEX #(WordSize) id_ex_latch(.clk(clk), .rstn(rstn), .branch_taken_in(branch_taken_in), .a_sel(a_sel), .b_sel(b_sel), .imm(imm), .pc_in(pc_in), .rs1d(rs1d), .rs2d_in(rs2d_in), .branch_addr_in(branch_addr_in), .rdn_in(rdn_in), .branch_taken(branch_taken), .rdn(rdn), .pc(pc), .branch_addr(branch_addr), .rs2d(rs2d), .a(a), .b(b)); | ||
logic [WordSize - 1:0] a, b; | ||
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Alu #(WordSize) alu_modulemake(.a(a), .b(b), .alu_mode(alu_mode), .alu_out(alu_out)); | ||
IDEX #(WordSize) id_ex_latch ( | ||
.clk(clk), | ||
.rstn(rstn), | ||
.branch_taken_in(branch_taken_in), | ||
.a_sel(a_sel), | ||
.b_sel(b_sel), | ||
.imm(imm), | ||
.pc_in(pc_in), | ||
.rs1d(rs1d), | ||
.rs2d_in(rs2d_in), | ||
.branch_addr_in(branch_addr_in), | ||
.rdn_in(rdn_in), | ||
.branch_taken(branch_taken), | ||
.rdn(rdn), | ||
.pc(pc), | ||
.branch_addr(branch_addr), | ||
.rs2d(rs2d), | ||
.a(a), | ||
.b(b) | ||
); | ||
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endmodule | ||
Alu #(WordSize) alu_modulemake ( | ||
.a(a), | ||
.b(b), | ||
.alu_mode(alu_mode), | ||
.alu_out(alu_out) | ||
); | ||
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endmodule |
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