Update Pipeline_Reset.sv

NYU-Processor-Design · Dec 4, 2023 · cb5162b · cb5162b
1 parent fa76b2e
commit cb5162b
Showing 1 changed file with 4 additions and 4 deletions.
diff --git a/rtl/Pipeline_Reset.sv b/rtl/Pipeline_Reset.sv
@@ -4,19 +4,19 @@ module Pipeline_Reset #(
   input [WordSize - 1:0] npc_in, npc_corr,
   input flush,
   output logic [WordSize - 1:0] npc,
-  output logic rstn
+  output logic rstn_out
 );
 
 always_comb begin
 case(flush)
 0: begin
     npc = npc_in;
-    rstn = 1'bZ;
+    rstn_out = 1'bZ;
 end
 1: begin
     npc = npc_corr;
-    rstn = 0;
+    rstn_out = 0;
 end
 endcase
 end
-endmodule
+endmodule