Revert "docs(10, 03_L1_Data_Cache.md): Updated Documentation"

This reverts commit 9fc0b01.

Documentation/01_Module_Docs/10_L1_Data_Cache.md

@@ -1,45 +1,41 @@
-# L1 Data Cache Outline
+# THIS MODULE IS NOT YET OUTLINED #
+
+# L1 Data Cache #
+(Any Notes would go here)
 
 ## Contents
 * [Inputs](#inputs)
 * [Outputs](#outputs)
 * [Functionality](#functionality)
   * [Registers](#registers)
-  * [On posedge clk](#on-posedge-clk)
-  * [Asynchronous active low reset](#asynchronous-active-low-reset)
+  * [Clk](#on-posedge-clk)
+  * [Active low reset](#asynchronous-active-low-reset)
 
 ## Inputs
-| Name              | Bits wide | Description                                  |
-|-------------------|:---------:|----------------------------------------------|
-| `clk`             | 1         | Clock input                                  |
-| `reset`           | 1         | Asynchronous active low reset input         |
-| `write_enable`    | 1         | Write enable signal                         |
-| `request_address` | 32        | Address for read or write operation         |
-| `write_data`      | 32        | Data to be written to the cache             |
+|Name|Bits wide|
+|:---|:---:|
+|```name```|#-bit|
+|```name```|#-bit|
 
 ## Outputs
-| Name            | Bits wide | Description                                  |
-|-----------------|:---------:|----------------------------------------------|
-| `response_data` | 32        | Data read from the cache                     |
+|Name|Bits wide|
+|:---|:---:|
+|```name```|#-bit|
+|```name```|#-bit|
 
 ## Functionality
-
 ### Registers
-| Name                  | Type         | Dimensions                       | Description                                  |
-|-----------------------|--------------|----------------------------------|----------------------------------------------|
-| `cache_data`          | 32-bit array | `[0:NO_OF_SETS-1][0:ASSOCIATIVITY-1]` | Data storage array in each cache set         |
-| `cache_tags`          | 32-bit array | `[0:NO_OF_SETS-1][0:ASSOCIATIVITY-1]` | Tag storage array in each cache set          |
-| `valid`               | 1-bit array  | `[0:NO_OF_SETS-1][0:ASSOCIATIVITY-1]` | Valid bit array indicating cache line status |
-| `dirty`               | 1-bit array  | `[0:NO_OF_SETS-1][0:ASSOCIATIVITY-1]` | Dirty bit array indicating modified data    |
-| `lru_counter`         | 32-bit array | `[0:NO_OF_SETS-1][0:ASSOCIATIVITY-1]` | LRU counter array for each cache set         |
-
+  - #-bit ```name``` register
+  - #-bit ```name``` register
 ### On posedge clk
-- Calculate cache set index: `set = (request_address / BLOCK_SIZE) % NO_OF_SETS;`
-- Determine cache hit or miss
-  - If hit, update `response_data` with cache data and reset LRU counter
-  - If miss, (not implemented for simplicity) fetch data from memory and update cache_tags, cache_data, and LRU counters
+  - ```somebranch = someval```
+  - Use a table when necessary if statements are used:
+  - ```name```
+    |Name|Bits wide|
+    |---|---|
+    |```name == 0```|```reg = val```|
+    |```name == 1```|```reg = val```|
+
 
 ### Asynchronous active low reset
-- Reset all LRU counters, dirty bits, and valid bits to initial values
-
-
+  - Register values reset to 0

Documentation/02_Complex_Module_Functions/03_L1_Data_Cache.md

@@ -1,58 +1 @@
-# L1 Data Cache Module Structure Overview Documentation
-
-### Inputs
-1. **`clk`**: System clock signal.
-2. **`reset`**: Reset signal for initializing the cache.
-3. **`request_address`**: A 32-bit input representing the memory address for read or write operations.
-4. **`write_data`**: A 32-bit input representing the data to be written to the cache.
-5. **`write_enable`**: An input signal to control write operations to the cache.
-
-### Outputs
-1. **`response_data`**: A 32-bit output representing the data read from the cache.
-
-## Functionality
-The `l1_data_cache` module is designed to provide a data caching mechanism that stores frequently accessed data to improve memory access speed. It operates based on the following functionality:
-
-### On Posedge
-
-The L1 Data Cache is a synchronous circuit, operating on a clock signal. On the positive edge (`posedge`) of the clock, the following operations are performed:
-
-- **Initialization**: On reset (`reset` signal), the cache is initialized, and the LRU counters and dirty bits are set to initial values.
-
-- **Write Operations**:
-  - When a write operation is enabled (`write_enable`), the module performs the following steps:
-    1. Determines the set index based on the request address.
-    2. Checks if the requested data is already in the cache.
-    3. If the data is present in the cache, it updates the cache with the new data, sets the dirty bit, and updates the LRU counter.
-    4. If the data is not in the cache, it may write back to memory (if the block being replaced is dirty), updates the tag, writes the data to the cache, sets the dirty bit, and updates the LRU counter.
-
-- **Read Operations**:
-  - When a read operation is requested, the module performs the following steps:
-    1. Determines the set index based on the request address.
-    2. Searches the cache for the requested data.
-    3. If the data is found, it updates the response data and updates the LRU counter.
-    4. If the data is not in the cache (a cache miss), it can fetch the data from the main memory and potentially implement write allocate.
-
-
-### Registers
-The module utilizes several registers to maintain cache state and metadata:
-
-- **`cache_data`**: A 3D array storing the data in the cache.
-- **`lru_counter`**: A 2D array representing the LRU counters for cache sets and blocks.
-- **`cache_tags`**: A 2D array storing the tag information for cache sets and blocks.
-- **`dirty_bit`**: A 2D array indicating whether the data in each block is dirty (needs to be written back to memory).
-
-### Combinational and Sequential Logic
-
-- The L1 Data Cache uses both combinational and sequential logic. Combinational logic is used for address decoding, tag comparison, and hit/miss detection. Sequential logic is used to store cache lines, implement the LRU replacement policy, and track the write-back status of cache lines.
-
-
-### Cache logic
-The cache should use the following logic:
-
-- **`Write allocate`**`:  When the processor writes data to the cache, the cache allocates a block from main memory and stores the data in the cache, even if the block is not currently needed.
-- **`Write back`**:       When the processor writes data to the cache, the cache updates the data in the cache and sets the dirty bit to high. The cache writes the data back to main memory only when the block is evicted from the cache or when the cache is flushed.
-- **`Lookthrough`**`:     When the cache misses, the cache fetches the block from main memory and stores it in the cache. The processor does not stall during this time, but the instruction that caused the cache miss is delayed.
-- **`LRU`**:              The LRU policy evicts the least recently used block from the cache when the cache is full.
-
-
+(Note: This document is currently incomplete)