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Interfaces: Fixed syntax #128

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merged 7 commits into from
Nov 20, 2023
Merged

Interfaces: Fixed syntax #128

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23cafa7
Update Int_Alu_Ops.sv
ShinyMiraidon Nov 20, 2023
f0ca5a2
Update Int_Branch_Manager_Input.sv
ShinyMiraidon Nov 20, 2023
2b4441e
Update Int_DCache_Manager_Control.sv
ShinyMiraidon Nov 20, 2023
2cb1245
Update Int_DReg_Info.sv
ShinyMiraidon Nov 20, 2023
f219bb0
Update Int_ID.sv
ShinyMiraidon Nov 20, 2023
ec9cc0d
Update Int_MEM.sv
ShinyMiraidon Nov 20, 2023
1e87925
Update Int_SReg_Nums.sv
ShinyMiraidon Nov 20, 2023
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4 changes: 2 additions & 2 deletions rtl/Int_Alu_Ops.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -5,10 +5,10 @@ interface Int_Alu_Ops #(
logic [WordSize - 1:0] a, b;

modport id_ex (
output [WordSize - 1:0] a, b
output a, b
);

modport alu (
input [WordSize - 1:0] a, b
input a, b
);
endinterface
6 changes: 2 additions & 4 deletions rtl/Int_Branch_Manager_Input.sv
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Expand Up @@ -6,13 +6,11 @@ logic [WordSize - 1:0] pc, addr;
logic taken;

modport id_ex (
output [WordSize - 1:0] pc, addr,
output taken
output pc, addr, taken
);

modport branch_manager (
input [WordSize - 1:0] pc, addr,
input taken
input pc, addr, taken
);

modport branch_predictor (
Expand Down
6 changes: 2 additions & 4 deletions rtl/Int_DCache_Manager_Control.sv
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Expand Up @@ -4,12 +4,10 @@ logic dcache_en, dcache_rw;
logic [1:0] data_mode;

modport general_control (
output dcache_en, dcache_rw,
output [1:0] data_mode
output dcache_en, dcache_rw, data_mode
);

modport con_mem {
input dcache_en, dcache_rw,
input [1:0] data_mode
input dcache_en, dcache_rw, data_mode
};
endinterface
6 changes: 2 additions & 4 deletions rtl/Int_DReg_Info.sv
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Expand Up @@ -6,12 +6,10 @@ logic [WordSize - 1:0] rdd;
logic [4:0] rdn;

modport mem_wb (
output [WordSize - 1:0] rdd,
output [4:0] rdn
output rdd, rdn
);

modport registers (
input [WordSize - 1:0] rdd,
input [4:0] rdn
input rdd, rdn
);
endinterface
8 changes: 3 additions & 5 deletions rtl/Int_ID.sv
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Expand Up @@ -6,16 +6,14 @@ logic [WordSize - 1:0] imm, pc;
logic [4:0] rdn;

modport if_id (
output [WordSize - 1:0] imm, pc,
output [4:0] rdn
output imm, pc, rdn
);

modport id_ex (
input [WordSize - 1:0] imm, pc,
input [4:0] rdn
input imm, pc, rdn
);

modport branch_addr_calc (
input [WordSize - 1:0] imm, pc,
input imm, pc,
);
endinterface
8 changes: 3 additions & 5 deletions rtl/Int_MEM.sv
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Expand Up @@ -6,17 +6,15 @@ logic [WordSize - 1:0] alu_out;
logic [4:0] rdn;

modport ex_mem (
output [WordSize - 1:0] alu_out,
output [4:0] rdn
output alu_out, rdn
);

modport mem_wb (
input [WordSize - 1:0] alu_out,
input [4:0] rdn
input alu_out, rdn
);

modport dcache_manager (
input [WordSize - 1:0] alu_out,
input alu_out,
);

endinterface
4 changes: 2 additions & 2 deletions rtl/Int_SReg_Nums.sv
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Expand Up @@ -3,10 +3,10 @@ interface Int_SReg_Nums();
logic [4:0] rs1n, rs2n;

modport if_id (
output [4:0] rs1n, rs2n
output rs1n, rs2n
);

modport registers (
input [4:0] rs1n, rs2n
input rs1n, rs2n
);
endinterface