batch: export FPGA IO width macro and merge output data for connection #579
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xiaokamikami
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klin02
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src/main/scala/Gateway.scala
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| @@ -271,12 +273,12 @@ object GatewaySink { | |||
| } | |||
| val out = Option.when(config.isFPGA) { | |||
| IO(new Bundle { | |||
| val batch = Output(chiselTypeOf(io)) | |||
| val data = Output(UInt()) | |||
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explicitly use width calculted in config
src/main/scala/Gateway.scala
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| @@ -55,7 +55,8 @@ case class GatewayConfig( | |||
| def maxStep: Int = if (isBatch) batchSize else 1 | |||
| def stepWidth: Int = log2Ceil(maxStep + 1) | |||
| def replayWidth: Int = log2Ceil(replaySize + 1) | |||
| def batchArgByteLen: (Int, Int) = if (isNonBlock || isFPGA) (3600, 400) else (7200, 800) | |||
| def batchArgByteLen: (Int, Int) = if (isFPGA) (1900, 100) else if (isNonBlock) (3600, 400) else (7200, 800) | |||
| def batchBitWidth: Int = if (isFPGA) 16000 else if (isNonBlock) 32000 else 64000 | |||
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calculated by byteLen above to make sure consistency
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When using fpga, the IO width information is exported to the macro definition file, and the info and data in the out are merged to facilitate direct connection to the transmission module
klin02
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Feb 25, 2025
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When using fpga, the IO width information is exported to the macro definition file, and the info and data in the out are merged to facilitate direct connection to the transmission module