VLSI Fault Simulator with Fault Collapsing

This is a Python-based tool, developed for the "VLSI Testing & Reliability" course at UIC (University of Illinois at Chicago), to simulate and analyze stuck-at faults in digital circuits.

The tool parses ISCAS-85 (.bench) circuit files and provides a framework for fault simulation and reduction.

Key Features

• Circuit Parser: Reads .bench files, decodes gates (AND, OR, NAND, XOR, etc.), and builds a levelized internal representation of the circuit graph.
• Fault Simulation Engine:
  • Performs "good" (fault-free) simulation to get a baseline correct output for a given input vector.
  • Injects specific stuck-at faults (output faults, branch faults) and runs "faulty" simulation to determine if the fault is detected (i.e., if the output differs from the "good" run).
• Fault Collapsing (Reduction):
  • Implements core logic-level fault reduction algorithms to minimize the initial fault list, making testing more efficient.
  • Fault Equivalence: Collapses faults based on gate logic (e.g., an input stuck-at-0 on an AND gate is equivalent to the output stuck-at-0).
  • Fault Dominance: Further reduces the list by applying dominance rules.

How to Run

First, install dependencies:

python -m venv venv
source venv/bin/activate 
pip install -r requirements.txt

Then:

1. Analyze a circuit (Fault Collapsing only)

python fault_simulator.py --circuit iscas85/c17.bench --verbose

2. Run Fault Simulation with an input vector

python fault_simulator.py --circuit iscas85/c17.bench --simulate 10101

Note: Ensure you have the ISCAS-85 benchmark files in the iscas85/ folder.

Example Output

[*] Loading circuit: iscas85/c17.bench...
=====================
   Circuit Summary   
=====================

Inputs
+-----+--------+
|   # |   Name |
+=====+========+
|   1 |      1 |
+-----+--------+
|   2 |      2 |
+-----+--------+
|   3 |      3 |
+-----+--------+
|   4 |      6 |
+-----+--------+
|   5 |      7 |
+-----+--------+

Outputs
+-----+--------+
|   # |   Name |
+=====+========+
|  10 |     22 |
+-----+--------+
|  11 |     23 |
+-----+--------+

Gates
+---------------+-------------+----------+---------+
|   Output Node | Gate Type   | Inputs   |   Level |
+===============+=============+==========+=========+
|            10 | NAND (2)    | 1, 3     |       1 |
+---------------+-------------+----------+---------+
|            11 | NAND (2)    | 3, 6     |       1 |
+---------------+-------------+----------+---------+
|            16 | NAND (2)    | 2, 11    |       2 |
+---------------+-------------+----------+---------+
|            19 | NAND (2)    | 11, 7    |       2 |
+---------------+-------------+----------+---------+
|            22 | NAND (2)    | 10, 16   |       3 |
+---------------+-------------+----------+---------+
|            23 | NAND (2)    | 16, 19   |       3 |
+---------------+-------------+----------+---------+
[*] Generating Fault List...
    - Total Raw Faults: 50
Initial Full Fault List:
1-0            11-3-0         19-0           22-10-0        23-19-0        
1-1            11-3-1         19-1           22-10-1        23-19-1        
10-0           11-6-0         19-11-0        22-16-0        23-OUT-0       
10-1           11-6-1         19-11-1        22-16-1        23-OUT-1       
10-1-0         16-0           19-7-0         22-OUT-0       3-0            
10-1-1         16-1           19-7-1         22-OUT-1       3-1            
10-3-0         16-11-0        2-0            23-0           6-0            
10-3-1         16-11-1        2-1            23-1           6-1            
11-0           16-2-0         22-0           23-16-0        7-0            
11-1           16-2-1         22-1           23-16-1        7-1            
    - Collapsed Faults: 16
    - Reduction Ratio: 68.00%

[*] Simulating with Input Vector: [1, 0, 1, 0, 1]
    - Good Output: ['22=1', '23=1']
[*] Running Fault Simulation on collapsed list...
    - Faults Detected: 4 / 16
    - Coverage: 25.00%