Standalone (offline) version of the Circuit Simulator with small modifications based on modified NW.js.

Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments

A platform for learning and experimenting with logic circuits

A simple digital logic simulator written as a learning exercise in C++

Full-timing gate-level logic simulator encoded entirely in C++ templates

billyprints is blueprints but with billy and without blue

Create simulated logic circuits with this online logic simulator

An ugly & interactive logic gate visualizer written in Java using plain old Java Swing

Windows application for designing and simulating digital logic circuits, written in C++ using CMU graphics library.

This is a simulation of a hundreed Rock Paper Scissors games where a computer logic plays with itself.

successor to my other logic simulator PygameLogicSim. This project separates the simulator into a front end and a back end

RiscV Environment for Simulation (R4VES) is a generic and modular framework that eases the grunt work required in order to perform pre/post-synthesis logic and fault simulation on RISC-V cores based on Model/QuestaSim and Z01X.

A simple digital logic simulator