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1. UART_V1 UART_V1 Public

   UART interface on an Artix-7 FPGA in Verilog, including FSM-based TX/RX logic, baud-rate generation, and framing control; validated through simulation and on-board testing.

   Verilog

2. Single-Cycle-RiscV-Core Single-Cycle-RiscV-Core Public

   Designed and implemented a RISC-V CPU (RV32I) in Verilog, integrating datapath and control logic to support arithmetic, load/store, and branch instructions; verified functionality through simulation.

   Verilog

3. MultiCycle-RISCV-Core MultiCycle-RISCV-Core Public

   SystemVerilog