GitHub - YogithL/UART_V1: UART interface on an Artix-7 FPGA in Verilog, including FSM-based TX/RX logic, baud-rate generation, and framing control; validated through simulation and on-board testing.

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UART_new.v		UART_new.v
uart_new_constraint.xdc		uart_new_constraint.xdc

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UART interface on an Artix-7 FPGA in Verilog, including FSM-based TX/RX logic, baud-rate generation, and framing control; validated through simulation and on-board testing.

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Verilog 79.6%
Tcl 20.4%

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