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Gowin. Fix BSRAM block selection. #1334

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Jul 3, 2024
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@yrabbit yrabbit commented Jun 27, 2024

In the images generated by Gowin IDE, the signals for dynamic BSRAM block selection (BLKSEL[2:0]) are not always connected directly to the ports - some chips add LUT2, LUT3 or LUT4 to turn these signals into Clock Enable. Apparently there are chips with an error in the operation of these ports.

Here we make such a decoder instead of using ports directly.

In the images generated by Gowin IDE, the signals for dynamic BSRAM
block selection (BLKSEL[2:0]) are not always connected directly to the
ports - some chips add LUT2, LUT3 or LUT4 to turn these signals into
Clock Enable.  Apparently there are chips with an error in the operation
of these ports.

Here we make such a decoder instead of using ports directly.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
@gatecat gatecat merged commit 0639681 into YosysHQ:master Jul 3, 2024
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2 participants