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[arch] support H618 Hello World app
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-[X] UART
-[X] CLK
-[X] SyterKit

TODO:
FIx sunxi_clk_dump
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@YuzukiTsuru
YuzukiTsuru committed Dec 26, 2023
1 parent 90258f2 commit 3a5a133
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Showing 13 changed files with 787 additions and 124 deletions.
12 changes: 7 additions & 5 deletions board/longanpi-3h/hello_world/main.c
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Expand Up @@ -7,20 +7,22 @@

#include <log.h>

#include <common.h>

#include <sys-dram.h>

extern sunxi_serial_t uart_dbg;

int main(void) {
sunxi_serial_init(&uart_dbg);

//sunxi_clk_init();
show_banner();

sunxi_clk_init();

//sunxi_clk_dump();
sunxi_clk_dump();

while (1) {
sunxi_serial_putc(&uart_dbg, 'H');
}
abort();

return 0;
}
201 changes: 177 additions & 24 deletions board/longanpi-3h/start.S
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@@ -1,17 +1,18 @@
/* SPDX-License-Identifier: Apache-2.0 */

#include <linkage.h>

#define ARMV7_USR_MODE 0x10
#define ARMV7_FIQ_MODE 0x11
#define ARMV7_IRQ_MODE 0x12
#define ARMV7_SVC_MODE 0x13
#define ARMV7_MON_MODE 0x16
#define ARMV7_ABT_MODE 0x17
#define ARMV7_UND_MODE 0x1b
#define ARMV7_SYSTEM_MODE 0x1f
#define ARMV7_MODE_MASK 0x1f
#define ARMV7_FIQ_MASK 0x40
#define ARMV7_IRQ_MASK 0x80
#define ARMV7_USR_MODE 0x10
#define ARMV7_FIQ_MODE 0x11
#define ARMV7_IRQ_MODE 0x12
#define ARMV7_SVC_MODE 0x13
#define ARMV7_MON_MODE 0x16
#define ARMV7_ABT_MODE 0x17
#define ARMV7_UND_MODE 0x1b
#define ARMV7_SYSTEM_MODE 0x1f
#define ARMV7_MODE_MASK 0x1f
#define ARMV7_FIQ_MASK 0x40
#define ARMV7_IRQ_MASK 0x80

.arm
.globl reset
Expand All @@ -23,43 +24,195 @@ reset:
.byte 'e', 'G', 'O', 'N', '.', 'B', 'T', '0'
.long 0x12345678 /* checksum */
.long __spl_size /* spl size */
.long 0x30 /* boot header size */
.long 0x30 /* boot header size */
.long 0x30303033 /* boot header version */
.long 0x00020000 /* return value */
.long 0x00028000 /* run address */
.long 0x0 /* eGON version */
.byte 0x00, 0x00, 0x00, 0x00 /* platform information - 8byte */
.long 0x0 /* eGON version */
.byte 0x00, 0x00, 0x00, 0x00 /* platform information - 8byte */
.byte 0x34, 0x2e, 0x30, 0x00

/*
* The actual reset code
*/
mrs r0, cpsr
bic r0, r0, #ARMV7_MODE_MASK
orr r0, r0, #ARMV7_SVC_MODE
orr r0, r0, #(ARMV7_IRQ_MASK | ARMV7_FIQ_MASK)
bic r0, r0, #(1<<9) @set little-endian
msr cpsr_c, r0

mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache
mcr p15, 0, r0, c1, c0, 0
/* Set vector base address register */

ldr r0, =_vector
mcr p15, 0, r0, c12, c0, 0
mrc p15, 0, r0, c1, c0, 0
bic r0, #(1 << 13)
mcr p15, 0, r0, c1, c0, 0

mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache
mcr p15, 0, r0, c1, c0, 0

/* Set stack pointer */
ldr sp, =__stack_srv_end

bl clear_bss
bl main

clear_bss:
/*
* disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,
* except if in HYP mode already
*/
mrs r0, cpsr
and r1, r0, #0x1f @ mask mode bits
teq r1, #0x1a @ test for HYP mode
bicne r0, r0, #0x1f @ clear all mode bits
orrne r0, r0, #0x13 @ set SVC mode
orr r0, r0, #0xc0 @ disable FIQ and IRQ
msr cpsr,r0

@set cntfrq to 24M
ldr r0, =24000000
mcr p15, 0, r0, c14, c0, 0

bl set_timer_count

bl main

clear_bss:
ldr r0, =_sbss
ldr r1, =_ebss
mov r2, #0

clbss_1:
clbss_1:
stmia r0!, {r2}
cmp r0, r1
blt clbss_1

mov pc, lr

_vector:
b reset
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
ldr pc, _data_abort
ldr pc, _not_used
ldr pc, _irq
ldr pc, _fiq

_undefined_instruction:
.word undefined_instruction
_software_interrupt:
.word software_interrupt
_prefetch_abort:
.word prefetch_abort
_data_abort:
.word data_abort
_not_used:
.word not_used
_irq:
.word irq
_fiq:
.word fiq

.macro save_regs
str lr, [sp, #-4]
mrs lr, spsr_all
str lr, [sp, #-8]
str r1, [sp, #-12]
str r0, [sp, #-16]
mov r0, sp
cps #0x13
ldr r1, [r0, #-4]
str r1, [sp, #-4]!
ldr r1, [r0, #-8]
str r1, [sp, #-(4 * 16)]
ldr r1, [r0, #-12]
ldr r0, [r0, #-16]
stmdb sp, {r0 - r14}^
sub sp, sp, #(4 * 16)
ldr r4, [sp]
and r0, r4, #0x1f
cmp r0, #0x10
beq 10f
cmp r0, #0x13
beq 11f
b .
11: add r1, sp, #(4 * 17)
str r1, [sp, #(4 * 14)]
str lr, [sp, #(4 * 15)]
10: add r1, sp, #(4 * 17)
str r1, [sp, #-4]!
mov r0, sp
.endm

.macro restore_regs
mov r12, sp
ldr sp, [r12], #4
ldr r1, [r12], #4
msr spsr_cxsf, r1
and r0, r1, #0x1f
cmp r0, #0x10
beq 20f
cmp r0, #0x13
beq 21f
b .
20: ldr lr, [r12, #(4 * 15)]
ldmia r12, {r0 - r14}^
movs pc, lr
21: ldm r12, {r0 - r15}^
mov r0, r0
.endm

/*
* Exception handlers
*/
.align 5
undefined_instruction:
sub lr, lr, #4
save_regs
bl arm32_do_undefined_instruction
restore_regs

.align 5
software_interrupt:
sub lr, lr, #4
save_regs
bl arm32_do_software_interrupt
restore_regs

.align 5
prefetch_abort:
sub lr, lr, #4
save_regs
bl arm32_do_prefetch_abort
restore_regs

.align 5
data_abort:
sub lr, lr, #8
save_regs
bl arm32_do_data_abort
restore_regs

.align 5
not_used:
b .

.align 5
irq:
sub lr, lr, #4
save_regs
bl arm32_do_irq
restore_regs

.align 5
fiq:
sub lr, lr, #4
save_regs
bl arm32_do_fiq
restore_regs
14 changes: 1 addition & 13 deletions cmake/board/longanpi-3h.cmake
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Expand Up @@ -7,13 +7,6 @@ set(CONFIG_BOARD_LONGANPI-3H True)

add_definitions(-DCONFIG_CHIP_SUN50IW9)

# Options

# By setting ENABLE_HARDFP to ON, it indicates that the project is configured
# to utilize hard floating-point operations when applicable. This can be beneficial
# in scenarios where performance gains from hardware acceleration are desired.
set(ENABLE_HARDFP OFF)

# Set the cross-compile toolchain
set(CROSS_COMPILE "arm-none-eabi-")
set(CROSS_COMPILE ${CROSS_COMPILE} CACHE STRING "CROSS_COMPILE Toolchain")
Expand All @@ -22,12 +15,7 @@ set(CROSS_COMPILE ${CROSS_COMPILE} CACHE STRING "CROSS_COMPILE Toolchain")
set(CMAKE_C_COMPILER "${CROSS_COMPILE}gcc")
set(CMAKE_CXX_COMPILER "${CROSS_COMPILE}g++")

# Configure compiler flags based on ENABLE_HARDFP option
if(ENABLE_HARDFP)
set(CMAKE_COMMON_FLAGS "-nostdlib -g -ggdb -O3 -mcpu=cortex-a53 -mthumb-interwork -mthumb -mno-unaligned-access -mfpu=neon-vfpv4 -mfloat-abi=hard")
else()
set(CMAKE_COMMON_FLAGS "-nostdlib -g -ggdb -O3 -mcpu=cortex-a53 -mthumb-interwork -mthumb -mno-unaligned-access -mfpu=neon-vfpv4 -mfloat-abi=softfp")
endif()
set(CMAKE_COMMON_FLAGS "-nostdlib -g -ggdb -O3 -mcpu=cortex-a53")

# Disable specific warning flags for C and C++ compilers
set(CMAKE_C_DISABLE_WARN_FLAGS "-Wno-int-to-pointer-cast -Wno-implicit-function-declaration -Wno-discarded-qualifiers")
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2 changes: 2 additions & 0 deletions include/drivers/sun50iw9/reg/reg-ccu.h
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Expand Up @@ -13,8 +13,10 @@
#define CCU_PLL_DDR1_CTRL_REG (CCU_BASE + 0x18)
#define CCU_PLL_PERI0_CTRL_REG (CCU_BASE + 0x20)
#define CCU_PLL_PERI1_CTRL_REG (CCU_BASE + 0x28)

#define CCU_PLL_HSIC_CTRL_REG (CCU_BASE + 0x70)


/* cfg list */
#define CCU_CPUX_AXI_CFG_REG (CCU_BASE + 0x500)
#define CCU_PSI_AHB1_AHB2_CFG_REG (CCU_BASE + 0x510)
Expand Down
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